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Found 3 results

  1. I am trying to interface PMOD DA4 with atlys FPGA but nothing is coming at output. help me to rectify what wrong with code. module spi_master_v1( input sys_clk, input rst, output reg cs, output reg MOSI, output reg sclk, // input [31:0] in_data, output reg done ); // Internal registers reg [10:0] count; reg [31:0] temp_data; reg [5:0] bit_count; reg [11:0] count2; // state declearation reg [1:0] state; parameter idle = 2'b00; parameter data_tx = 2'b01; parameter finish = 2'b10; //initialize all register initial begin cs = 1; MOSI = 0; sclk = 0; done = 0; count = 0; temp_data =32'b00000000000000000000000000000000; bit_count = 0; state = 0; count2 = 0; end // clock dividwer always @(posedge sys_clk) begin if (count == 4) begin sclk <= ~sclk; count <= 11'b00000000000; end else begin count = count +1; end end // functional design always @(posedge sclk) begin case (state) idle : begin done = 1'b0; cs = 1'b1; state = data_tx; temp_data[7:0] = 8'b00000000; temp_data[19:8] = count2; temp_data[31:20] = 12'b100000001111; MOSI = 0; count2 = count2 + 1; end data_tx: begin cs = 1'b0; MOSI = temp_data[31-bit_count]; if (bit_count == 32) begin state = finish; bit_count = 0; done = 1'b1; MOSI = 0; end else begin bit_count = bit_count + 1; end end finish: begin cs = 1'b1; state = idle; MOSI = 0; end endcase end endmodule
  2. Hello, I am Raghu, doing my Master Thesis. I am using Zedboard to emulate few sensor's signals. I have already implemented DA1 and AD2 on to Zedboard and connected in the loop. They both work perfectly fine. But next step was to implement DA4 in my design, and I didn't find any drivers for the same. So I tried using normal AXI SPI IP in the hardware design for DA4 and tried to develop my own driver (considering DA1's driver as an example). All the initialization part works perfectly fine and the communication also takes place as per DA4's datasheet. But when it is asked to send data, it is not sending the exact data. Any help regarding the same would be very helpful. Please find the attached for my complete SDK project and a separate Program file. DA_4.zip DA_4_Prog.zip
  3. Hello, I have recently purchased Zedboard along with Pmods AD1 and DA4. I want to implement Gradient Descent algorithm in the Zedboard using these Pmods with bandwidth more than 100 kHz. To get started, I tried to regenerate a analog signal using the Pmods AD1 and DA4. The experiment is completely explained with block design and output plots in the ADC_DAC_1_compressed.pdf. The SDK C code for acquistion and generation (adc_dac.c) as well as for finding max. working speed of DAC (dac_maxv.c) are atttached. The ADC clk is set to 20 MHz and DAC clk is to 50 MHz. It could be observed from the ADC_DAC_1_compressed.pdf that the maximum speed (frequency) the DAC (DA4) can write is only 33 kHz. The desirable acquisition and generation rate should be more than 200 kHz for my case. I identified that, the Xspi transfer written in the code (adc_dac.c) sends only 8 bits out of 32 bits of the DAC per clock cycle. Can we directly write all the 32 bits of the DAC in a single clk cycle using SDK ?? or is there any other way to make the ADC and DAC work faster?? What am I missing?? Looking forward to you suggestions and other similar references. Thanks in advance