Constraints and Bitstream generation

[MsDh]

Hello all,

I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board (part#: xc7z020clg484) and familiar with Verilog modules/test bench as beginner. 

I've created a top module with an output 8-bit bus (OUTPUT) and multiple inputs. My inputs are CLK (from main clock of the board), RESET (push button), ENA (ON/OFF switch), stpGo (stop and go push button).

Inside my top module I've three sub-modules instantiated and connected to each other. I created a constraint file to connect all the ports to the necessary switches or buttons on my ZedBoard Zynq-7000.

Here is my constraint file:

# Clock Source - Bank 13
set_property PACKAGE_PIN Y9 [get_ports {CLK}]; # "GCLK"
# ----------------------------------------------------------------------------
# User LEDs - Bank 33
set_property PACKAGE_PIN T22 [get_ports {OUTPUT[0]}]; # "LD0"
set_property PACKAGE_PIN T21 [get_ports {OUTPUT[1]}]; # "LD1"
set_property PACKAGE_PIN U22 [get_ports {OUTPUT[2]}]; # "LD2"
set_property PACKAGE_PIN U21 [get_ports {OUTPUT[3]}]; # "LD3"
set_property PACKAGE_PIN V22 [get_ports {OUTPUT[4]}]; # "LD4"
set_property PACKAGE_PIN W22 [get_ports {OUTPUT[5]}]; # "LD5"
set_property PACKAGE_PIN U19 [get_ports {OUTPUT[6]}]; # "LD6"
set_property PACKAGE_PIN U14 [get_ports {OUTPUT[7]}]; # "LD7"

# User Push Buttons - Bank 34
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN P16 [get_ports {RESET}]; # "BTNC"
set_property PACKAGE_PIN R16 [get_ports {stpGo}]; # "BTND"

# ----------------------------------------------------------------------------
# User DIP Switches - Bank 35
# ---------------------------------------------------------------------------
set_property PACKAGE_PIN F22 [get_ports {ENA}]; # "SW0"
#set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1"
# ---------------------------------------------------------------------------
# IOSTANDARD Constraints
# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard.
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
# Set the bank voltage for IO Bank 34 to 1.8V by default.
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
# Set the bank voltage for IO Bank 35 to 1.8V by default.
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets stpGo_IBUF];

My constraint file is looking at my top-module ports only. I thought my other modules are internally connected and don't have to create constraint files for each of them separately. I am using Vivado 2018.2 software and I have attached the screenshots helping you to understand me better.

Part#: xc7z020clg484-1 or ****-2 getting the same result.

I restarted the Vivado and ran synthesize and implementation in order to generate Bitstream. Before all these steps I used this command to set Bitstream version check to "False" in my Tcl consul. After Bitstream generation was completed successfully (as system reported) I went to program my device but no Bitstream file was showing in dialog box to open. I browsed and selected a .bit file in my impl_1 folder called CountingLED.bit. I had the same error messages after I ran "Program".

Please refer to images and let me know if I am not clear enough.

Thank you for your helps in advance.

[JColvin]

Hi @MsDh,

Luckily, I think I see the problem.

xc7z020clg484-1 is the correct part for the Zedboard, but as your project settings show, you actually have the 7014 part selected, not the 7020 Zynq chip. Once you change that, everything should be good to go.

Thanks,
JColvin

P.S. In the future, you can help avoid accidents like this by installing board files where you can directly select the board name during the initial project creation and it will already have the correct part chosen for you. Let me know if you have any questions on how to do this.

[JColvin]

Hi @MsDh,

I have moved your question to a more appropriate section of the Forum (since the Zedboard is not a microcontroller).

From what you have said and shown, it looks like you have set the correct board and the TCL console appears to think it's the right one, but could you show a screenshot of what device Vivado thinks is being used? You can find it via the Project Manager->Settings->General tab. What revision of the Zedboard do you have?

Thanks,
JColvin

[MsDh]

Hi, thanks for correction and updates.

My Zedboard revision is D. My general settings is as shown in the picture, using part #:xc7z020clg484-2 OR xc7z020clg484-1

Please refer to the images and let me know if I am following you properly.

 

[MsDh]

JColvin,

Thanks for your help. My first FPGA simple project is working now. I can now move forward to start another project. I appreciate your help.

Have a nice day, stay safe.

Masoud