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Found 19 results

  1. suung33

    zybo z7-10 I2C master

    Hello, I'm a student studying about FPGA. I want to get an analog signal by processing the digital signal output from the zybo through the i2c. (I will use tca9548a and mcp4725 for DAC) To do this, I want to make sure that there is a digital signal from zybo-z7 through i2c. I made a block design using Axi_iic IP, and set the SCL to JE1(V12) and the SDA to JE2(W16) through the constraints file. After that, I ran the ‘xiic_selfftest_example.c’ code through Vitis. After connecting jumper wires to JE1 and JE2, the oscilloscope measured the voltage and found that both(SCL, SDA) output 3.3V. However, there is no change from 3.3V (High) to 0V (Low). I know that i2c communication starts when SDA becomes low, but the project I designed is not. Q1) Is i2c communication not started because the i2c slave device(ex. tca9548a) is not connected to zybo? If this is correct, how do I specify the Slave address? (Is it designated by the C code in vitis?) Q2) Do I need to run code other than " xiic_selfftest_example.c " to start i2c communication? (Is there an example code to start i2c communication?) Q3) I designed using only block design, but is it necessary to create a separate Verilog code for i2c communication? Q4) I set the pull-up resistance on the FPGA through the constraints file, is this not enough? (Do I have to connect a separate resistance?) Can this be the reason that output is not a digital signal? Ps: I purchased a Pmod (Pmod AD2, Pmod CMPS2) using i2c bus to learn i2c communication. Can I understand i2c communication by practicing how to use these pmod? I am attaching the Block design, constraints code, and oscilloscope measurement results of JE1(SCL) pin. Thanks.
  2. Hi We have Digilent 1.64 installed in a few machines. Does anyone know if Digilent is affected by or has mitigation advice for : https://www.zdnet.com/article/security-warning-new-zero-day-in-the-log4j-java-library-is-already-being-exploited/ Thank you
  3. I know the likely answer is no - due to limits of and script looping in terms of window timer etc accuracy. But I'm always surprised by the capability in this thing. But any simple way to do a PI loop closure ? Like measure on CH1 and CH2 and command? It can certainly do "seconds" for things like temp control but I'm looking for less than 10 ms delay lag.
  4. Xilinx Digilent Spartan-3E Starter Kit 410-087 On Ebay https://www.ebay.com/itm/Xilinx-Digilent-Spartan-3E-Starter-Kit-410-087/283549512750?
  5. Hi everyone, I downloaded digilent.waveforms_3.2.6_armhf.deb and installed it on my system. The "dwfcmd" command is working fine and the python examples also work. Now I want to compile the C examples and I keep getting errors: analogin_trigger.c:(.text+0x74): undefined reference to `FDwfDeviceOpen' analogin_trigger.c:(.text+0x9c): undefined reference to `FDwfGetLastErrorMsg' analogin_trigger.c:(.text+0xd4): undefined reference to `FDwfAnalogInFrequencySet' analogin_trigger.c:(.text+0xec): undefined reference to `FDwfAnalogInBufferSizeSet' analogin_trigger.c:(.text+0x110): undefined reference to `FDwfAnalogInChannelEnableSet' analogin_trigger.c:(.text+0x128): undefined reference to `FDwfAnalogInChannelRangeSet' analogin_trigger.c:(.text+0x13c): undefined reference to `FDwfAnalogInTriggerAutoTimeoutSet' analogin_trigger.c:(.text+0x154): undefined reference to `FDwfAnalogInTriggerSourceSet' analogin_trigger.c:(.text+0x168): undefined reference to `FDwfAnalogInTriggerTypeSet' analogin_trigger.c:(.text+0x17c): undefined reference to `FDwfAnalogInTriggerChannelSet' analogin_trigger.c:(.text+0x190): undefined reference to `FDwfAnalogInTriggerLevelSet' analogin_trigger.c:(.text+0x1a4): undefined reference to `FDwfAnalogInTriggerConditionSet' analogin_trigger.c:(.text+0x1f4): undefined reference to `FDwfAnalogInConfigure' analogin_trigger.c:(.text+0x208): undefined reference to `FDwfAnalogInStatus' analogin_trigger.c:(.text+0x248): undefined reference to `FDwfAnalogInStatusData' analogin_trigger.c:(.text+0x2dc): undefined reference to `FDwfDeviceCloseAll' I used clang and gcc to build the analogin_trigger.c sample: clang analogin_trigger.c Where is my mistake?
  6. Hi im getting these warnings while i try to validate design in Vivado while executing hello world program which makes use of Zynq 7000 boards. i kindly request you to give a siolution for these warnings [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values.
  7. I bought a Digilent HS2 USB programmer along with a C-Mod C2 for a project I'm working on. All goes well until I try to program the bitstream into my device using IMPACT in ISE. When I plug the HS2 into the USB port, Linux recognizes the device and I can open the Cable Communication Setup dialog. I have installed the Digilent USB package and so I see my device listed in the Port field. But anytime I try to do anything other than open this dialog, like program the device, it just hangs or runs super slowly without actually doing anything. I tried this both plugged into the C-Mod or not and the behavior is the same. As another data point I also have a CoolRunner-II board with the built in programmer and that works fine on the same Linux box. I'm unclear on what's going on or how to diagnose or correct it. Any thoughts?
  8. DIGILENT Analog Discovery 2 USB Oscilloscope & Instrumentation System On Ebay https://www.ebay.com/itm/DIGILENT-Analog-Discovery-2-USB-Oscilloscope-Instrumentation-System/265008360732?
  9. Digilent The XUP Virtex 2 Pro Engineering Development Board, NOS On Ebay https://www.ebay.com/itm/Digilent-The-XUP-Virtex-2-Pro-Engineering-Development-Board-NOS/293335649993?
  10. Digilent Zybo Z7 Zynq-7010 Arm FPGA SoC Platform On Ebay https://www.ebay.com/itm/Digilent-Zybo-Z7-Zynq-7010-Arm-FPGA-SoC-Platform/313133597855?
  11. Digilent The XUP Virtex 2 Pro Engineering Development Board, NOS On Ebay https://www.ebay.com/itm/Digilent-The-XUP-Virtex-2-Pro-Engineering-Development-Board-NOS/293335649993?
  12. Digilent ZedBoard: Zynq-7000 ARM/FPGA SoC Development Board ENG On Ebay https://www.ebay.com/itm/Digilent-ZedBoard-Zynq-7000-ARM-FPGA-SoC-Development-Board-ENG/283937508675?
  13. National Instruments Digilent NI myRIO 1900 Student Edition w/ box & accessories On Ebay https://www.ebay.com/itm/National-Instruments-Digilent-NI-myRIO-1900-Student-Edition-w-box-accessories/254395258339?
  14. Hello all, I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board (part#: xc7z020clg484) and familiar with Verilog modules/test bench as beginner. I've created a top module with an output 8-bit bus (OUTPUT) and multiple inputs. My inputs are CLK (from main clock of the board), RESET (push button), ENA (ON/OFF switch), stpGo (stop and go push button). Inside my top module I've three sub-modules instantiated and connected to each other. I created a constraint file to connect all the ports to the necessary switches or buttons on my ZedBoard Zynq-7000. Here is my constraint file: # Clock Source - Bank 13 set_property PACKAGE_PIN Y9 [get_ports {CLK}]; # "GCLK" # ---------------------------------------------------------------------------- # User LEDs - Bank 33 set_property PACKAGE_PIN T22 [get_ports {OUTPUT[0]}]; # "LD0" set_property PACKAGE_PIN T21 [get_ports {OUTPUT[1]}]; # "LD1" set_property PACKAGE_PIN U22 [get_ports {OUTPUT[2]}]; # "LD2" set_property PACKAGE_PIN U21 [get_ports {OUTPUT[3]}]; # "LD3" set_property PACKAGE_PIN V22 [get_ports {OUTPUT[4]}]; # "LD4" set_property PACKAGE_PIN W22 [get_ports {OUTPUT[5]}]; # "LD5" set_property PACKAGE_PIN U19 [get_ports {OUTPUT[6]}]; # "LD6" set_property PACKAGE_PIN U14 [get_ports {OUTPUT[7]}]; # "LD7" # User Push Buttons - Bank 34 # ---------------------------------------------------------------------------- set_property PACKAGE_PIN P16 [get_ports {RESET}]; # "BTNC" set_property PACKAGE_PIN R16 [get_ports {stpGo}]; # "BTND" # ---------------------------------------------------------------------------- # User DIP Switches - Bank 35 # --------------------------------------------------------------------------- set_property PACKAGE_PIN F22 [get_ports {ENA}]; # "SW0" #set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1" # --------------------------------------------------------------------------- # IOSTANDARD Constraints # Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]]; # Set the bank voltage for IO Bank 34 to 1.8V by default. set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]]; # Set the bank voltage for IO Bank 35 to 1.8V by default. set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]]; # Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets stpGo_IBUF]; My constraint file is looking at my top-module ports only. I thought my other modules are internally connected and don't have to create constraint files for each of them separately. I am using Vivado 2018.2 software and I have attached the screenshots helping you to understand me better. Part#: xc7z020clg484-1 or ****-2 getting the same result. I restarted the Vivado and ran synthesize and implementation in order to generate Bitstream. Before all these steps I used this command to set Bitstream version check to "False" in my Tcl consul. After Bitstream generation was completed successfully (as system reported) I went to program my device but no Bitstream file was showing in dialog box to open. I browsed and selected a .bit file in my impl_1 folder called CountingLED.bit. I had the same error messages after I ran "Program". Please refer to images and let me know if I am not clear enough. Thank you for your helps in advance.
  15. National Instruments Digilent NI myRIO 1900 Student Edition w/ box & accessories On Ebay https://www.ebay.com/itm/National-Instruments-Digilent-NI-myRIO-1900-Student-Edition-w-box-accessories/254395258339?
  16. Xilinx Digilent Spartan-3 FPGA Device board On Ebay https://www.ebay.com/itm/Xilinx-Digilent-Spartan-3-FPGA-Device-board/333444326757?
  17. Digilent Spartan-3E Xilinx Starter Kit FPGA Development Board On Ebay https://www.ebay.com/itm/Digilent-Spartan-3E-Xilinx-Starter-Kit-FPGA-Development-Board/352889427005?
  18. Digilent Xilinx XUP Virtex-II Pro Development System On Ebay https://www.ebay.com/itm/Digilent-Xilinx-XUP-Virtex-II-Pro-Development-System/132336841558?
  19. If you hear of or author a textbook featuring a Digilent product, we want to know about it! So far, we have the following list compiled: Digital Design Using Digilent FPGA Boards Verilog/Active -HDL Edition by Haskell & Hanna Introduction to Digital Design Using Digilent FPGA Boards- VHDL Edition by Haskell & Hanna PIC32 Microcontrollers and the Digilent chipKIT: Introductory to Advanced Projects by Ibrahim Real Digital: A Hands-on Approach to Digital Design by Cole FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version by Chu Getting Started with chipKIT: The Arduino Compatible PIC32 Based Module by Hellebuyck Synthesis and Optimization of FPGA-Based Systems by Sklyarov & Skliarova iLab Analog by Chen Yun Chao Digital Fundamentals by Floyd The Zynq Book by Crockett, Elliot, Enderwitz, Stewart Beginning C for Arduino by Purdum Electrical Engineering Practicum by Bowman FPGA Based System Design by Memon, Hassan & Memon Introduction to Electric Circuits 9th edition, by Jackson/Temple/Kelly
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