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Found 7 results

  1. I have a ZedBoard (Zynq XC7Z020) on which I wish to prototype some software on a MicroBlaze that will eventually be moved to a ZCU-102, and ultimately to a custom IO card. I was given the ZedBoard and installed the Xilinx software that came with it, but ISE 14.1 seems to have some trouble with Windows 10 (file selection dialogs don't always appear, and it can't seem to talk to the network very well), so I've installed Vivado 2021.1. Unfortunately, none of the directions I've found for installing the board files work properly under this version of the tools - it seems the stuff on GitHub (XilinxBoardStore / XilinxCEDStore) are not supported (I can't get them to work following the directions I've found, at least), and when I tried editing the Vivado start-up tcl script, the XML files appear available on the Diligent site seem to be incompatible (it breaks Vivado), so I cannot seem to create a project for the ZedBoard using Vivado 2021.1. There is a very nice Wiki page on the Diligent site that describes how to do it for the 2019 edition of the Xilinx tools, but it's out of date. Can anyone offer some advice on what I should do? Should I uninstall Vivado (both the 2021.1 and 14.1 versions) and try to download and install something in-between? This is on a Windows 10, 64-bit host. Thanks in advance. Sorry about typos and odd spacing (I've tried to clean it up as I type), but the laptop keyboard I'm using is not agreeing with my fingers, and I keep typing the wrong keys and extra spaces.
  2. so i created this project , to display the video from camera OV7670 through VGA on my Zedboard , only using the PL part , the synthesis runs good but i when i try to generate the bitstream i get these errors that i can't seem to understand : error 1 : [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pclk_IBUF] > pclk_IBUF_inst (IBUF.O) is locked to IOB_X0Y43 and pclk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y7 error 2 : [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. error 3 : [Common 17-69] Command failed: Placer could not place all instances here is a link where you should find everything you need if you you want to take a look : www.github.com/moncefou/camera_vga_zedboard
  3. I would like to integrate PMOD NIC100 with Microzed board with Zynq 7020 running on linux. I have a SPI interface routed through the PL logic. Are there any IP that can be directly imported to Vivado for this ? OR Are there any drivers that can be installed on the linux ? Please suggest.
  4. Hi all, Maybe it's just a small detail that is missing but I don't know how to solve it exactly. I’m trying to communicate my laptop with my ZedBoard but for some reason, it suddenly stops. I follow the procedure indicated in instructions included with the ZedBoard package and are also indicated in this tutorial. I download the USB to UART adapter driver (controller version 3.13.0.59) by Cypress which controls the USB serial port (in this case COM9). The device is identified as Cypress-USB2UART-Ver1.0G. The settings form COM9 are like the figures. When I turn on the ZedBoard with the SD Card boot configuration, my laptop detects the new device, the green power led turns on (LD13), a few seconds later the DONE blue led turns on (LD12) and the MI07 led turns on (LD9) but later it turns off and at the end the LD11 flicker for a few second. In the TeraTerm terminal appears the instructions and commands which indicates that the booting starts but it stops at line [ 1.130000] (see image). I tried to start the communication independently through Matlab using the command: hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'Toolpath', 'D:\Vivado\2019.1\bin\vivado.bat'); And next, to communicate with the ZedBoard I used the instruction z = zynq which show the following error message: -------- Error using codertarget.zynq.internal.LinuxShell/setupZynqHardware (line 574) Cannot connect to "Zynq hardware". Details: Could not connect to the hardware over Serial Port. Check that USB cable is plugged into 'USB-to-UART' port of the hardware and the power switch is turned on. If this error persists, switch off the hardware, wait for 10 seconds, switch on the hardware and then repeat this step. Error in codertarget.zynq.internal.LinuxShell (line 212) obj.setupZynqHardware(username,password,remotedir); Error in zynq (line 113) h = codertarget.zynq.internal.LinuxShell('ZC702', varargin{:}); --------- I really don’t know what exactly is going on, the error indicates that’s probably a driver issue, but I checked the drivers and it seems that all was installed correctly, and they are the proper versions. Maybe, the problem could be from the SD card files, which are back-up files that I downloaded from the Digilen webpage additional resources in the zip file named “zedboard_oob_design.zip”. How we can check if the SD card files are ok? If the problem is in the drivers so, what is the proper driver version which works in this case? I’m using Windows 10, 64 bits, processor x64, with Matlab R2019b and Vivado 2019.1 For Matlab with FPGA applications, I have the following toolboxes: Embedded Coder, HDL Coder, and HDL Verifier. Please I really need help with this issue, I cannot finish my project if I cannot communicate with the card with the UART. --Eduardo
  5. Hello all, I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board (part#: xc7z020clg484) and familiar with Verilog modules/test bench as beginner. I've created a top module with an output 8-bit bus (OUTPUT) and multiple inputs. My inputs are CLK (from main clock of the board), RESET (push button), ENA (ON/OFF switch), stpGo (stop and go push button). Inside my top module I've three sub-modules instantiated and connected to each other. I created a constraint file to connect all the ports to the necessary switches or buttons on my ZedBoard Zynq-7000. Here is my constraint file: # Clock Source - Bank 13 set_property PACKAGE_PIN Y9 [get_ports {CLK}]; # "GCLK" # ---------------------------------------------------------------------------- # User LEDs - Bank 33 set_property PACKAGE_PIN T22 [get_ports {OUTPUT[0]}]; # "LD0" set_property PACKAGE_PIN T21 [get_ports {OUTPUT[1]}]; # "LD1" set_property PACKAGE_PIN U22 [get_ports {OUTPUT[2]}]; # "LD2" set_property PACKAGE_PIN U21 [get_ports {OUTPUT[3]}]; # "LD3" set_property PACKAGE_PIN V22 [get_ports {OUTPUT[4]}]; # "LD4" set_property PACKAGE_PIN W22 [get_ports {OUTPUT[5]}]; # "LD5" set_property PACKAGE_PIN U19 [get_ports {OUTPUT[6]}]; # "LD6" set_property PACKAGE_PIN U14 [get_ports {OUTPUT[7]}]; # "LD7" # User Push Buttons - Bank 34 # ---------------------------------------------------------------------------- set_property PACKAGE_PIN P16 [get_ports {RESET}]; # "BTNC" set_property PACKAGE_PIN R16 [get_ports {stpGo}]; # "BTND" # ---------------------------------------------------------------------------- # User DIP Switches - Bank 35 # --------------------------------------------------------------------------- set_property PACKAGE_PIN F22 [get_ports {ENA}]; # "SW0" #set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1" # --------------------------------------------------------------------------- # IOSTANDARD Constraints # Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]]; # Set the bank voltage for IO Bank 34 to 1.8V by default. set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]]; # Set the bank voltage for IO Bank 35 to 1.8V by default. set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]]; # Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets stpGo_IBUF]; My constraint file is looking at my top-module ports only. I thought my other modules are internally connected and don't have to create constraint files for each of them separately. I am using Vivado 2018.2 software and I have attached the screenshots helping you to understand me better. Part#: xc7z020clg484-1 or ****-2 getting the same result. I restarted the Vivado and ran synthesize and implementation in order to generate Bitstream. Before all these steps I used this command to set Bitstream version check to "False" in my Tcl consul. After Bitstream generation was completed successfully (as system reported) I went to program my device but no Bitstream file was showing in dialog box to open. I browsed and selected a .bit file in my impl_1 folder called CountingLED.bit. I had the same error messages after I ran "Program". Please refer to images and let me know if I am not clear enough. Thank you for your helps in advance.
  6. I'm using Vivado 2019 and a Zedboard, trying to implement "HelloWorld" in PS and output "Hello World" at PC terminal.but it doesn't work. usb-uart and usb-jtag is connected with PC (Win10) i'm using mio-46,47 to uart0 please help me... my step: 1. vivado open block design > HDL wrapper 2. run implementation 3.Export Hardware 4. launch SDK > new application project 5. open putty for monitor (COM4, speed is 115200) 6. SDK run configuration and the setting as following > Run 7. run result as following 8. the com port terminal is nothing... please let me know where i do the wrong step.. thank you very much.!!!
  7. Hello While I was working on ZedBoard with USB-JTAG, the USB port suddenly broke apart. When I contact the USB port pins with the board pins, I can still do stuff, but I want this port to be fixed to the board. So I requested RMA to my seller but she told me that the warranty period is over and guided me to post a question in this forum. I bought the board on Oct 05, 2018. Any way to get this broken port fixed?