Genesys 2 DDR Constraints

[SeanS]

Hello,

I am working with the Genesys 2 FPGA board and I have downloaded the master xdc constraints from here:

https://github.com/Digilent/digilent-xdc/blob/master/Genesys-2-Master.xdc

But there doesn't appear to be any constraints for the DDR3.

I downloaded the Out of the Box demo and in the Genesys2_H.xdc file there appears the following note: 

#_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-

#　 For DDR constraints please refer to our website

#_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-

Where can I find the pin, level, and timing constraints for the DDR3 peripheral interface?

 

-Sean

[jpeyron]

Hi @SeanS,

Did you install the Digilent board files as discussed above? In project creation make sure to select the boards you are using. The digilent board files become the default settings when you do block automation with added IP Cores like microblaze and the MIG. I have added a screen shot of the MIG setting that was automatically generated because of the board files.

best regards,

Jon

[jpeyron]

Hi @SeanS,

Welcome to the Digilent Forums!

The DDR3 has its own constraint file provided in the board files called the mig.prj.

Here is a link to a forum question that addresses this situation just on a different board.

Here is the mig.prj for the Genesys 2

Here is a tutorial on board file installation. 

best regards,

Jon

[SeanS]

Thanks for the info!  That explains it perfectly.

 

-Sean

[SeanS]

I have a follow up question.  I read through the solution for the Arty board but I couldn't find a way to add the mig.prj file to a new scratch project.

I attempted to instantiate a mig_7series_0 instance in my project, followed by a configuration of it by double clicking the block.  When prompted, I entered the path to the mig.prj file I downloaded from the git repository.  Unfortunately, it doesn't look like the tool found the Bank Number, Byte Number, Pin Number, IO Stadard and VCCAUX PD values in the prj file.

The dialog lists the signal names, but not the remaining parameters.  Is there something obvious I am missing here?  Is there a preferred way to add existing IP to a project?

 

 

 

 

[JColvin]

Hi @SeanS,

Jon and I looked at this a bit further, and it looks like you are using ISE rather than Vivado. Is there a particular reason you are using ISE rather than Xilinx's newer Vivado software? Otherwise, my understanding is that you would need the UCF file loaded with the correct information (as per the legacy ISE material we have for the Genesys and MIG tutorial here). However, the Genesys 2 was developed and released a few years after the last formal release of ISE, so we do not have a UCF file for the Genesys 2 available (nor do we have the appropriate details in the .xdc file thanks to the existence of the board files for Vivado.

Thanks,
JColvin

[SeanS]

Hi JColvin,

I am definitely not using ISE.  I think JPeyron had it correctly.  I didn't have my board.Repopaths variable set and so the project wasn't finding the board files.  Once I set this variable as suggested, the pin mapping and IO types were auto populated as expected.

Kudos,

Sean

 

[jpeyron]

Hi @SeanS,

@JColvin response was also my thoughts based on the screen shot. The color scheme of the MIG page attached looks like ISE. 

I am glad that you are now able to get the MIG default setting to be pre-set by the board files.

best regards,

Jon