Accessing all the data and to store in wire using BLOCK RAM GENERATOR in Vivado using verilog

[Sandeep I]

I've created a block ram generator(single port ROM) in vivado using a coe file in verilog. I'm able to read the values one at time using continuous statement(able to instantiate rom block once a clock pulse). Here is my snippet:
   
    module coedata(clk,rst,a);
    input clk,rst;
    output  [31:0]a;
    wire[12:0]addra,out;
    wire [31:0]douta ;
    count c1(clk,rst,out); // just gives count in 'out' to access address(addra)
    assign addra=out;
    blk_mem_gen_0 your_instance_name (
      .clka(clk),    // input wire clka
      .addra(addra),  // input wire [12 : 0] addra
      .douta(douta)  // output wire [31 : 0] douta
    );
    assign a=douta;
    endmodule

This is ok. I can read value through instantiating once a clock. But I want to store all these values into 2D wire such as [31:0] a[0:100].I want all the values to be available in one clock pulse.(Just assume we have created a sufficient ROM block)

    module coedata(clk,rst);
    input clk,rst;
    reg  [31:0]a[0:99];
    wire[12:0]addra,out;
    wire [31:0]douta ;
    count c1(clk,rst,out,i); // just gives count in 'out-binary' to access,'i-integer' address(addra)
    assign addra=out;
    blk_mem_gen_0 your_instance_name (
      .clka(clk),    // input wire clka
      .addra(addra),  // input wire [12 : 0] addra
      .douta(douta)  // output wire [31 : 0] douta
    );
    assign a=douta;
    endmodule

It is saying that 'i' is not a constant.

Thanks in advance.

[jpeyron]

Hi @Sandeep I,

It  looks like you are not declaring what 'i' is i.e. wire, reg.... and you should be giving it an initial value.

thank you,

Jon

[Sandeep I]

Thanks @jpeyron. I did a few mistakes in declaration. I have declared a as register and I used continuous statement and in continuous statement we can't declare a where i is not a constant.