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JColvin

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Posts posted by JColvin

    Recording Math Functions

    in Test and Measurement

    Posted

    I do not believe this is possible to do "live" so-to-speak with the on-board hardware to get a notch filter for 50/60 Hz. You can do this with external passive components of course or a Math Channel, though the Math Channel is done in software. Outside of exporting a completed acquisition, I do not think it is readily possible to record Math channel data directly to a file.

    Let me know if you have any questions.

    Thanks,
    JColvin

    PowerBRICKS ripple

    in Add-on Boards

    Posted

    Hi @BryanP,

    Yes, I had actually gotten a reply the next day, but clearly forgot to inform you of the response. As an upfront detail, the engineer was not able to locate any validation documents on the PowerBRICKs themselves, so this is what they would expected based on the topology:

    Quote

    [1/13/23 12:37 AM]

    Hi James, the best I could do was to look up the controller IC datasheets and see the typical measurements presented in there.

    These power supplies are all asynchronous, they have a diode as second switch; therefore all will operate in discontinuous conduction below a certain load current threshold. In these cases the ripple will be larger since the supply is skipping cycles.

    According to the datasheets and to the larger theoretical ripple on boost and buck-boost converters, I would say that the customer can expect something between 10mV and 20mV typical ripple + the AC noise caused by the load steps.

    The PowerBRICK schematics are not available (not my choice), so I'm not able to provide any additional information beyond this. If I can find the original Word document, I'll see if I can get this information added into the Reference Manual (or create a reference manual on the Reference site that is akin to other existing reference manuals, presuming that I get some time to dig into this and also not forget for a year).

    Hope this helps.

    Thanks,
    JColvin

    Analog Discovery 3 WaveForms - Automotive Measurements - Custom Probes Needed Please

    in Test and Measurement

    Posted

    Hi @JonD,

    The Eclypse Z7 is compatible with WaveForms; you'll need to configure a microSD as explained in the Help tab, but you'll be able to use both Zmod Scopes:

    image.png

    image.png

    As for the different style of plots, I don't believe those exact styles of plots of supported, but there is a Persistence view within the Scope that does show multiple waveforms within the same view:

    image.png

    With device buffering, WaveForms will capture up to 10k of the previous acquisitions that you can individually view, but I don't believe you can readily layer them directly within WaveForms in any of the ways you displayed.

    Attila (the WaveForms developer) may have some more insight (they are in a different timezone, so it might be awhile before a response).

    Let me know if you have any questions.

    Thanks,
    JColvin

    AD3 appearing in device manager but not detected by Waveforms

    in Test and Measurement

    Posted

    Hi @nanderson,

    I don't have any insight into WaveForms reacting to the ValueCAN 3 module that you mentioned, but I have the following questions/would try the following things:

    - Are you connected to a USB hub of some kind? If you running the AD3 through an external (unpowered) hub that has other devices on it that are also competing for power draw, that could cause some issues.
    Newer versions of the WaveForms software (starting with 3.21.15 onwards) add support within the WaveForms Device Manager to have a notification for when a low supply voltage is detected.

    - If connecting to a different/more direct USB port doesn't work (or external power supply), it would probably be worth trying a different cable to help eliminate that source of error, though needing to wiggle the connector to get the LED to turn on is not expected.

    Since Windows is detecting the device, a lack of power seems like the most likely issue to me.

    Let me know what you learn.

    Thanks,
    JColvin

    Analog Discovery 3 Powering Options

    in Test and Measurement

    Posted

    Hi @O.T.,

    1) Yes, you can power the Analog Discovery 3 with a USB Type C with Power Delivery; I usually power my device either in this way or through a USB Standard A port that supports the USB 3.x power requirements (in my personal, anecdotal, experience, most standard A ports that are internally connected to a USB 3.x controller are able to supply up to 900 mA without complaint). 

    2) A 5 Volt 4 Amp external supply would be able to power the Analog Discovery 3 at its most power intensive state.
    I have also used a 5 Volt 2.5 Amp supply to run the Analog Discovery 3 without having the USB connected (you can change the device behavior within the "On Close" option inside the Options dropdown within the WaveForms Device manager), though in that particular instance I was not using the Power Supplies so I was not at risk of overdrawing the external supplies.

    3) I am not aware of any additional information outside of the Power Requirements section you referred to in the Specifications (https://digilent.com/reference/test-and-measurement/analog-discovery-3/specifications#power_requirements) or the somewhat inferred material within the LED States section of the Reference Manual (https://digilent.com/reference/test-and-measurement/analog-discovery-3/reference-manual#led_states) that shows whether or not the device has been fully powered on.
    I will see about adding in a section in the Reference Manual that adds some additional information about power requirements for the device; thank you for the feedback.

    Let me know if you have any questions.

    Thanks,
    JColvin

    Basys3 autoconnect on Vivado 2023

    in FPGA

    Posted

    Hi @taitashaw,

    I haven't worked with HLS specifically, but the troubleshooting steps for getting the Basys 3 successfully detected by the Vivado software is explained in more detail in this thread here:

    As for the 2023.2 differences in terms of the flow differences between this and previous versions (since Digilent's guide for setting up a basic project with Vivado and Vitis is based on 2023.1 and earlier) I would recommend checking out Adam Taylor's post on the differences between the flow here: https://www.adiuvoengineering.com/post/microzed-chronicles-introducing-vitis-unified-ide.

    Let me know how it goes for you.

    Thanks,
    JColvin

    NEW ADP 3450 Still having issues "DstmTransfer failed ERC: 3077"

    in Test and Measurement

    Posted

    I wanted to let you know that I have seen your question, but I am waiting for the WaveForms developer (Attila, who was working with you on an earlier thread) to return to the office to offer more support as this particular set of errors that you have seen is outside my realm of knowledge.

    The only thing I can readily think of that I don't believe has been directly brought up or clarified would be to use a USB port directly present on a computer as opposed to a USB hub that is also simultaneously supporting a number of additional devices.

    Thanks,
    JColvin

    Restore ZedBoard factory booting

    in FPGA

    Posted

    Hi @mvernengo,

    What revision of the Zedboard do you have? Neither the Rev D nor the Rev F of the Zedboard that I have match the silkscreen image you posted with the Mode numbering (my two versions list the MIO numbers), though the jumper numbering (JP7..11) does match. My concern is that if the jumper numbering is identical that then the Mode[X] silkscreen labels would not readily line up with the orientation listed in Table 18 of the Zedboard User Guide that Avnet created here: https://digilent.com/reference/_media/reference/programmable-logic/zedboard/zedboard_ug.pdf.

    Presuming the latter situation, your setup of Mode3 and Mode2 being set high would have the device boot from Quad SPI flash memory (which is based on Mode2 high, and both Mode1 and Mode0 low), which from my understanding is not loaded or prepared by default with the Out-Of-Box material. That would be loaded through the SD card image (Boot Modes 2 and 1 set to logic high), which you can find in the Zedboard Resource Center here: https://digilent.com/reference/programmable-logic/zedboard/start#additional_resources.

    I would also put Mode3 to logic low to set the device to Cascaded JTAG rather than Independent JTAG so that you can more readily access the device as per Table 22 in above linked user guide.

    As for the serial terminal not responding in readable characters, my gut reaction would be to double check the baud rate (by default Zynq designs use 115200 baud, but Tera Term uses 9600 baud by default).

    Let me know what you find out.

    Thanks,
    JColvin

    Subtract scope channels

    in Test and Measurement

    Posted

    Hi @doggy,

    The Analog Input Channels on the Analog Discovery 3 have overvoltage protection to +/- 50 V DC (or +/- 30 V RMS) as per the last row in the Vertical System table here https://digilent.com/reference/test-and-measurement/analog-discovery-3/specifications#analog_input_channels, so you should be fine (relatively speaking) with the +/- 24 V system, particularly if the supply is being inherently limited.

    You are correct that when using the BNC probes each of the analog inputs will then be single ended. You can add a Math channel through the "Add Channel" dropdown on the right hand side and set it up to do C1 minus C2 like you asked about. There is some additional information about the Math Channels in Section 3.6 of the Scope section of the Help tab.

    image.png

    Let me know if you have any questions.

    Thanks,
    JColvin

    About PCAM_5C_SCH drawing

    in FPGA

    Posted

    Hi @RggBer,

    I have reached out to an engineer more familiar with the Pcam 5C regarding the specifics on how the OV5640 chooses internal vs external powering (I can't readily find the answer based on the datasheet that I found online here), but they are out of office until next week.

    Otherwise, there is a recommended power up sequence that is mentioned in the refererence manual here: https://digilent.com/reference/add-ons/pcam-5c/reference-manual#power-up_and_reset.

    Thanks,
    JColvin

    WaveForms Logic Analyzer: can't find a way to filter glitches?

    in Test and Measurement

    Posted

    Hi @Alrie,

    I'm not certain what you might have as a triggering setup, but presuming that these Chip Select glitches aren't the software unintentionally toggling the CS line and using something like a weak pulldown resistor doesn't work in your situation, you can use the Pulse/Timeout to have it only trigger low CS negative pulses that exceed some length of time:

    Let me know if that works for you (or if it doesn't quite work for your system so we can troubleshoot further).

    Thanks,
    JColvin

    Power down sequence in a FPGA(Arty S7 board)

    in FPGA

    Posted

    Hi @Prabhat.kumar

    My understanding (I have not explicitly verified this with the design engineer of the Arty S7) is that the board does not directly respect the recommended power-down sequence, only the power-up sequence that is mentioned in DS189: https://docs.xilinx.com/r/en-US/ds189-spartan-7-data-sheet/Power-On/Off-Power-Supply-Sequencing.

    I imagine this was done partially because the datasheet does not say it "must" be followed (theory based on this thread: https://support.xilinx.com/s/question/0D52E000078vhPbSAI/for-spartan-7-poweroff-sequence-is-it-required-or-we-can-just-pull-the-plug-according-to-ds189-the-recommended-poweroff-sequence-is-the-reverse-of-the-poweron-sequence-does-not-say-its-required?language=en_US and https://support.xilinx.com/s/question/0D52E00006iHkiJSAS/power-down-sequence-of-artix-7-and-power-up-sequence-of-spartan-6?language=en_US) and partially because Digilent cannot readily prevent users from 'pulling the plug' to suddenly and unexpectedly disconnect power from the board.

    Thanks,
    JColvin

    Forum Guilelines

    in Suggestions & Feedback

    Posted

    I agree that the organization of content on the Digilent Forum (and various other Digilent owned websites) are not an ideal state. Peeking behind the curtain, it is a goal of ours to identify, prioritize, and execute on a number of documentation clean up tasks during our "spare time"; I'll make sure that Project Vault and Tutorials subforums are included in this effort as well.

    Thank you for the feedback,
    JColvin

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