attila

I thank you for the observation. The Help/Script was correct but the tip in the status bar was wrong.

Hi @baldengineer Use: Supplies.Output.Output1.Enable.value = 1;

Hi @rtorsvik The setup should work since the measurements are done on the Scope inputs. Take in consideration the 1M of the inputs.

Hi @MRMTZ For repeated captures the single acqmode should be used. The record is for continuous streaming at lower rate. The record with small amount of samples, up to device buffer size, should behave similar to single. This is broken in 3.20.1 but it should work again in the latest version:

Hi @rtorsvik The 1+ should be connected to the W1, this is done in the IA adapter, to measure the exact output of the W1 for reference, since precise phase and amplitude are important when measuring the second node with 2+ The scope inputs are 1M, so if you are not using additional reference resistor you can enter a huge number, like 1T Ohm in the Calibration dialog. See a follow-up on related post:

Hi @zygot

Hi @skuznicki The DmgtConfigureFPGA was added in 2021.12.1 adept version 2.26.1 I always recommend using the latest. https://digilent.com/reference/software/adept/runtime-previous-versions

Hi @JAlaj When capturing up to DIN15 the USB bandwidth may be sufficient, 19*500kHz*32bit = 38MBps but I'm not sure if the data processing can keep up with it. The resulting record to file after 24hours would be more than 8TB !

Hi @JAlaj The sampling rate Logic Analyzer should be more at least twice of the SPI clock frequency ! Only the SPI transfers in the loop function are packed ! The loop Rate should be less than SPI Frequency/ SPI bits in loop cycle ! above 8-9MHz for 16bit * 500kHz Do you want to read or write or.. ? Currently the Protocol only supports the 16 DIOs. I could add support for DINs as input but the data streaming need for 500kHz rate (72MBps) is beyond the USB bandwidth (45MBps). At this rate the device memory is sufficient only for about one minute.

Hi @reddish Thank you for your comment. I'll try to allocate a few days, weeks... for the manual. I've been planning to rewrite it in a simpler and more detailed html format for a long time.

Hi @Shalin You are sending a 32 bit command to MOSI, followed by a 16 bit write|read to MOSI|MISO Do you need 32bit command ? not a 16bit one ? Do you also to have to read at the same time the MISO ? not in a separate transfer ? Is the SPI mode correct ?

Hi @reddish @zygot, AD3 topology is similar to AD2 but better. A dedicated low-jitter PLL (CDCE6214) is used to drive the ADC and DAC. By default (standalone/master) the PLL uses a local oscillator, providing to ADC a clock with less than 3ps jitter in 50Hz and 20MHz range. A PLL in the FPGA is used to generate internal clocks, and also a low frequency clock which can be adjusted (10-50MHz) and optionally output on the Trigger IOs. The device can also be used with external reference clock of 10-50MHz (slave) applied to Trig1, bypassing the FPGA and driving the dedicated PLL. With 10MHz reference clock we measured less than 4ps jitter on ADC clock relative to the reference. The reference clock minimum is limited to 10MHz due to the PLL specs. New users are usually overwhelmed by the features available, often saying it's too much... only to request another feature a few minutes later. The SPI functions were designed so the CS is controlled by software, but we had several requests for hardware-controlled CS, which is why the Cmd variants were added.

Hi @JAlaj See the Help tab Exactly what transfers do you have to do ? could you post your script ?

Hi @Shalin See the various Source options, events or the SPI channel, but for logging the interpreted SPI transfers better use the Protocol/SPI/Spy The Logic events got fixed in the latest version v3.20.27 It was broken earlier after introducing the variable capture resolution to allow 64bit captures, "Scope to Digital" digitization...

Hi @skuznicki The AD3 is only supported by WF 3.19.40 or newer which requires adept 2.26.1 or newer

Hi @Marvin1 See the WF SDK/ samples/ py/ AnalogOut_Sync.py AnalogOut_Phase.py examples Use the least common multiple of signal periods for FDwfAnalogOutRunSet and use FDwfAnalogOutRepeatSet 0 for infinite repeat.

Hi @Carl Troili This must a bottleneck in the USB 'firmware' or driver, when transferring 1024 bytes, 2 USB packets

Hi @skuznicki digilent.adept.runtime Depends: libc6 (>= 2.23), libusb-1.0-0, avahi-daemon, libavahi-common3, libavahi-client3 digilent.waveforms: Depends: libc6 (>=2.23), xdg-utils, digilent.adept.runtime (>=2.26.1), libqt5multimedia5-plugins, libqt5scripttools5, libqt5network5...

Hi @abedbaltaji With AD2 repeated captures up to 8192/16384 are supported at up to 100MHz and longer/continuous data streaming up to about 2.5MHz

Hi @reddish 1,2,3,6 should be fixed in the latest version: Have to look at 4,5 later Thank you for your posts.

Hi @qwertylex In the Scope interface Add Channel/ Digital/ or View menu/Digital or use the Digital button in the toolbar. After this, if you want to show digital signals in the analog plot you can Add Custom Math channel and use the digital channel names. The digital input logic threshold is about 1.5V so the 1.8V signals may not be detected correctly. You could help a bit with pull-up enabled from the Device options, like from the statusbar, the "100MHz" button, or Settings/Options/...

Hi @JAlaj See the Example menu

Hi @JAlaj The ~1ms delay is the software latency for each transfer call. You can use the Sensor tab which packs multiple transfers in one.

Hi @roshy Use the following when changing the DIOs: FDwfDigitalSpiClockSet(hdwf, 9) # clock on DIO-9 .... read/write FDwfDigitalOutEnableSet(hdwf, 9, 0) # disable (float, high impedance) earlier clock output on DIO-9 FDwfDigitalSpiClockSet(hdwf, 1) # clock on DIO-1 ... read/write FDwfDigitalOutEnableSet(hdwf, 1, 0) # disable DIO-1 ... If you want to drive low or high, use the following instead of disable: FDwfDigitalOutCounterInitSet(hdwf, 9, 0 or 1, 0) FDwfDigitalOutCounterSet(hdwf, 9, 0, 0)

Hi @Carl Troili It may be useful for you project the high resolution trigger time available with AD3, see the AnalogIn_Trigger.py example.