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Found 7 results

  1. Hello, I need help I work on the pmodgyro, and I've been trying to get the temperature for several days but I can't. I use the stm32. and I even tried with the arduino it does not work. I think I may have fried it as I use i2c communication and I often fail to use resistane pull-up. I would like to have concrete suggestions to test the sensor please, Thank you
  2. I am trying to use the PmodCAN module together with PetaLinux on the ZedBoard, to display a CAN interface within the OS. So far I can make it show up in the interface overview with the following device tree overlay: /* <petalinux-project-root>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi */ /include/ "system-conf.dtsi" / { osc: can_osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <20000000>; }; }; &gpio0 { #interrupt-cells = <2>; interrupt-controller; }; &spi1 { is-decoded-cs = <0>; num-cs = <1>; status = "okay"; spidev@0x00 { compatible = "microchip,mcp25625"; spi-max-frequency = <10000000>; clocks = <&osc>; interrupt-parent = <&gpio0>; interrupts = <0 0x2>; reg = <0>; } }; I can even send and receive messages using `candump` and `cansend`, but the interface behaves strange together with some CAN libraries. E.g. Messages are sometimes not sent, when the library tries to send multiple messages without any delay between them. On the other hand, when I connect the PmodCAN to a RaspberryPi and use same said libraries, everything works fine. So the only difference I can see between the working Raspberry Pi and the "strange" behaving Zynq setup, is the manually defined device tree overlay you see above. Long story short: Is my device tree overlay for the PmodCAN correct, to use it together with the ZedBoard on the JE Pmod connector? Maybe there is even a template somewhere? Based on the issues I have, I suspect something might be wrong with the clock and frequency definitions ...
  3. Hi Everyone! I need help using the following pmodi2s2 module: - https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ I want to use it to sample audio data from microphone only. So, I've added the i2s receiver IP into my block diagram (attached) and run block automation. Following is the documentation of the IP core I used: - https://www.xilinx.com/support/documentation/ip_documentation/i2s/v1_0/pg308-i2s.pdf The following is a reference manual for the above mentioned PMOD module: - https://reference.digilentinc.com/pmod/pmodi2s2/reference-manual I also created an extra clock in PL fabric named FCLK_CLK1 (11.289MHz requested and got 11.290323 MHz). I couldn't find a PMOD core for the said module so I guessed I'll "make-external" and "constraint" the pins on to the PMOD header in a .xdc file. Now, I don't know what to connect where except for the lrclk_out, sclk_out and sdata_0_in which are obvious from their names. Rest of the configuration is auto generated by block automation. I'm particularly confused regarding the clocking and reset configuration. Please help me out on this I'll highly appreciate.
  4. I'm trying to get the Pmod Color module for the Zynq z7-10 to work but it doesn't appear to be on. I was following along the instructions from these sites: https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start https://projects.digilentinc.com/arthur-brown/displaying-color-readings-with-the-pmod-color-and-python-ebd794 and I have it connect to the device as such on the board's JA port: Following along with the first link, I skipped the steps where a clock and interrupt were added as the data sheet shows that the Pmod Color IP does not require these. I have included my schematic below. I see that the module has an LED pin (LD1) but it doesn't appear to be on when connected to my powered device. In the SDK, I added a debug 'else' statement to the main() portion of the code to see if the Pmod is receiving data. After running the code on the board, the else statement is the only statement being executed. What could be the issue that my module is not turning on? I took a voltmeter reading, and the Vcc and GND pins are getting 3.3V. Following the instructions of the first link, I noticed they never included a constraints file. Could this be the issue? zynq_ps_main_c.c
  5. Hi Im using Zybo 7020 Vivado/Vitis 2020 and i have some errors on Vitis when i compile the hw platform. "Running Make libs in ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src" make -C ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta rtfiles -g -Wall -Wextra" make[2]: Entering directory 'C:/Users/NZT/workspace/Gyrotest/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src' "Compiling PmodGYRO..." arm-none-eabi-ar: *.o: Invalid argument make[2]: *** [Makefile:19: libs] Error 1 make[1]: *** [Makefile:30: ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src/make.libs] Error 2 make: *** [Makefile:30: zynq_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a] Error 2 make[2]: Leaving directory 'C:/Users/NZT/workspace/Gyrotest/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src' make[1]: Leaving directory 'C:/Users/NZT/workspace/Gyrotest/zynq_fsbl/zynq_fsbl_bsp' Building the BSP Library for domain - standalone_domain on processor ps7_cortexa9_0 "Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_7/src" "Compiling gpiops" "Running Make libs in ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src" make -C ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta rtfiles -g -Wall -Wextra" "Compiling PmodGYRO..." arm-none-eabi-ar: *.o: Invalid argument make[1]: *** [Makefile:19: libs] Error 1 make: *** [Makefile:30: ps7_cortexa9_0/libsrc/PmodGYRO_v1_0/src/make.libs] Error 2 Failed to build the bsp sources for domain - standalone_domain Failed to generate the platform. Reason: Failed to build the zynq_fsbl application. invoked from within "::tcf::eval -progress {apply {{msg} {puts $msg}}} {tcf_send_command tcfchan#0 xsdb eval s es {{platform active Gyrotest; platform generate }}}" (procedure "::tcf::send_command" line 4) invoked from within "tcf send_command $::xsdb::curchan xsdb eval s es [list "platform active $PLATFORM_NAME; platform generate $target"]" invoked from within "if { $iswindows == 1 } { set XSDB_PORT [lindex $argv 0] set PLATFORM_NAME [lindex $argv 1] set arglen [llength $argv] set lastind..." (file "C:/Xilinx/Vitis/2020.1\scripts\vitis\util\buildplatform.tcl" line 11) I thinks there is some problems in the makefile the error comes from this line in makefile $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} I downloaded the Library from github
  6. Hello, I am Raghu, doing my Master Thesis. I am using Zedboard to emulate few sensor's signals. I have already implemented DA1 and AD2 on to Zedboard and connected in the loop. They both work perfectly fine. But next step was to implement DA4 in my design, and I didn't find any drivers for the same. So I tried using normal AXI SPI IP in the hardware design for DA4 and tried to develop my own driver (considering DA1's driver as an example). All the initialization part works perfectly fine and the communication also takes place as per DA4's datasheet. But when it is asked to send data, it is not sending the exact data. Any help regarding the same would be very helpful. Please find the attached for my complete SDK project and a separate Program file. DA_4.zip DA_4_Prog.zip
  7. Hello, I have recently purchased Zedboard along with Pmods AD1 and DA4. I want to implement Gradient Descent algorithm in the Zedboard using these Pmods with bandwidth more than 100 kHz. To get started, I tried to regenerate a analog signal using the Pmods AD1 and DA4. The experiment is completely explained with block design and output plots in the ADC_DAC_1_compressed.pdf. The SDK C code for acquistion and generation (adc_dac.c) as well as for finding max. working speed of DAC (dac_maxv.c) are atttached. The ADC clk is set to 20 MHz and DAC clk is to 50 MHz. It could be observed from the ADC_DAC_1_compressed.pdf that the maximum speed (frequency) the DAC (DA4) can write is only 33 kHz. The desirable acquisition and generation rate should be more than 200 kHz for my case. I identified that, the Xspi transfer written in the code (adc_dac.c) sends only 8 bits out of 32 bits of the DAC per clock cycle. Can we directly write all the 32 bits of the DAC in a single clk cycle using SDK ?? or is there any other way to make the ADC and DAC work faster?? What am I missing?? Looking forward to you suggestions and other similar references. Thanks in advance