Hello everyone,
I created an IP core that uses axi4-stream interface with 4 hls::streams, two of them use the "typedef ap_axis<32,0,0,0> AXI_INT;" and the other two use the "typedef hls::axis<double,4,5,5> AXI_DOUBLE;". I had no problems creating the design in HLS and Vivado.
However, when I try to run the block in Vitis, I noticed I'm not able to send more than 4096 elements to both of the streams, even though I specified their depth as 9886 and 4853 respectively. Why do I have this problem? I'm using the simple mode of AXI DMA. Line 178 of vitis works sucessfuly (because I send up to 4096 elements) but the transfer right below (line 185) gets stuck forever.
I send in attachment some pictures of the design.
Thanks for all the attention and time!