Gonçalo Pinho

Hi artvvb, My design already has the widht of buffer length register maxed for both DMA's (picture below). The problem is, looking at the first transfer, I'm able to send the 4096 elements of the "TxBuffer_Int_Ptr" without a problem. However, as soon as I try to send one more value (the second XaxiDMAsimpletransfer), I instantly get stuck in the line "while(XAxiDma_Busy(&axiDMA_0,XAXIDMA_DMA_TO_DEVICE))". I went inside the line function "XAxiDma_SimpleTransfer(&axiDMA_0,(UINTPTR) TxBuffer_Int_Ptr+4096, 4096*sizeof(int), XAXIDMA_DMA_TO_DEVICE)" just to check and the length of my transfer (16384 bytes) is indeed smalller than the "TxBdRing.MaxTransferLen" (in this case is 67108863 bytes because I maximized the widht of the buffers to 26 bits). What else could be changed to solve the issue? Thanks for the time

Hello everyone, I created an IP core that uses axi4-stream interface with 4 hls::streams, two of them use the "typedef ap_axis<32,0,0,0> AXI_INT;" and the other two use the "typedef hls::axis<double,4,5,5> AXI_DOUBLE;". I had no problems creating the design in HLS and Vivado. However, when I try to run the block in Vitis, I noticed I'm not able to send more than 4096 elements to both of the streams, even though I specified their depth as 9886 and 4853 respectively. Why do I have this problem? I'm using the simple mode of AXI DMA. Line 178 of vitis works sucessfuly (because I send up to 4096 elements) but the transfer right below (line 185) gets stuck forever. I send in attachment some pictures of the design. Thanks for all the attention and time!