Brogli

A month ago I got everything to work and then the exam weeks came around, so I forgot to inform you. Thank you for your help. It is much apprechiated.

In January I finally could work on it for two full weeks instead of roughly half a day per week like before. Luckily I got the ADC to run as well as my own SPI port for the DAC. So could make a voltage follower where a picoscope compared the signal from the signal generator and the one going through the FPGA. It worked quite well and shouldn't be the Bottleneck in my future project. My next step is making a webserver on the linux part of the FPGA. But for this part I have a coworker who knows how to do it and I can use some of his files for reference. So I hopefully don't need any help from the forum. The IP block of the ADC is still in his default settings though. If that causes any errors then I will have to spend some time playing around with them.

Did you manage to get it to run?

@zygot I agree with you. I have stumbled on a different problem and created a new tread for that. So far nobody has taken a look at it. Would you be so kind and check, if you can give me any hints on how to proceed there?

To close out this comment thread, I have built my own IP for the SPI and it works now. Thank you for the help and the thoughts you had additional to the specific problem.

Hello Everybody I have an Eclypse Z7 with a Zmod Scope 1410-105s and use Vivado 2020.2 to program it. I tried to read out the analog input by using the IP block ZmodScopeController. For that I used the document "Zmod Scope Controller IP Core User Guide" and the software code of "Eclypse Z7 Low-Level Low-Pass Filter Demo" as a reference. I managed to start up the IP. At least the two signals "sInitDoneADC" and "sInitDoneRelay" are on HIGH and the two signals "sConfigError" and "sDataOverflow" are on LOW. When I read out the value of "cDataAxisTdata" then it is 0 all the way down. So no low level noise or flickering. Just a pure 0. Then I thought perhaps you need to load a buffer. So I put both "cDataAxisTready" and "sEnableAcquisition" on a slow clock. But this doesn't change anything. Additional inputs and outputs of the IP are as follows: SysClk100 = 100MHz ADC_SamplingClk = 40MHz ADC_InClk = 80MHz aRst_n=HIGH sTEST Configuration data: Sampling Clock Period [ps] = 25000 ADC Data Width = 14 ADC Clock Divide Ratio = 2 All checks are disabled I have a signal on the ADC which can switch between 0V, 1.65V and 3.3V. I checked the Hardware and both the hardware and software accesses the ZMOD A port/card. I want to be able to read something with this ADC and IP and I run out of ideas on what I should try. Can anyone give me some hints on where I should look to make it run? I would love to provide additional information if it helps in finding out what is missing.

Thank you again for our response. I'm sorry for writing in a confusing manner. Part of it certainly is because I'm new to designing my own FPGA control system. But I could give more attention to write in a clear manner anyways. I do have 2 Zmod Scope 1410-105s, so I'm pretty sure I got all three of the analogue inputs covered. Also for our first implementation I've learned that the guy responsible for the electronics accidentally did a cutoff of 1MHz instead of 10MHz and I don't think they see the need for increasing that in the next milestone. Another thing is that they failed to measure 2 out of the 3 signals. Their newly designed sensory circuit is considerably more sensitive, so I assume they will bring it up to 2 out of 3 sensors being useable at the end of the milestone, but no tests have been done yet. Also apparently the only goal for the next milestone is to just observe with no closed loop control yet, so the output is not necessary for now. I still want to implement it though so that my effort later on will be smaller. The improvement to the target specifications will happen in a later iteration. And if I notice that this hardware has some non-solvable limits I can probably buy a new one when the time comes. You got it correct that my analog input signal bandwidth of interest is between 0 and 10 MHz. Based on what I've heard, a 500 KHz analog output bandwidth should work well enough too. At the moment I'm still in the proof of concept phase and I don't see any problems with being off by a factor of only 2. I don't think it makes sense to make my own DAC circuit. The goal of the control system is to take noisy input signals and based on that do some simple controlling of an output signal. The device to be controlled can take a new command signal every 1μs. As the sensors who observe the system are very noisy I want to oversample the input signals. The oversampling is there purely for noise reduction. So theoretically the two don't have to by synchronous at all. I can have two entirely seperate systems, one for signal analysis and one for the control system, and they communicate with an asynchronous "virtual port". I'm aware, that if I needed just a simple first order low pass filter with a cuttoff frequency of 1MHz, then that oversampling would not be needed and a hardware lowpassfilter would suffice. But one step in that controll circuit needs to have a very fast reaction time. We do not know yet if a first order low pass filter is fast enough for that. I have the hope that with a smart way of signal control, it is possible to shorten my reaction time in case it is needed. I have to talk with other people from the school about that aspect of the task. But for the current milestone this is not yet relevant. I do not know enough about the storage needs of my control system and the storage capabilities which Eclypse Z7 can offer. Also I have not used any of Digilent's higher level sources. With higher level sources do you mean petalinux? For my first milestone petalinux is not needed. For later steps of the project it will be needed, but I have someone I can contact who knows about that aspect of the development. In the end my project might be integrated into his project. So I don't worry about this for now.

Hello @zygot I use the Eclypse Z7 which has a clock of 125MHz. And there two SYZYGY™ Ports which are built for the Zmod Scopes. Sadly it only has double ADC or double DAC extension cards and no card with one ADC and one DAC. So I have to use a DAC over the PMOD port. My inputs should be at 10MHz and the output at 1MHz. I'm not sure yet how strong the requirement is when it comes to the number of needed bits. But I assume they are pretty lax with the output and might be a bit higher in the inputs. Based on the comment from Arthur I assume that I will need to replace the DAC for a faster one. But first I want to make it run. When it comes to the prototype it does not matter if the device is a bit too slow as long as I get the proof of concept running. The final implementation will be different anyways and not an islotated system like mine is currently. Do you see any possible conflicts when it comes to bandwidth? Thank you too, Philipp Brogli

Hello @artvvb Thank you for the explanation. Thank you for the reference to the demo project. In the meantime I looked a bit at the datasheet of the AD5541A and I think the effort of viewing that demo project is too big compared to the effort of reading the relevant timings from the datasheet. When I wrote that comment I lost myself a bit in the documents searching for a proper IP. Physically the Pmod and the Zmod do not collide. I already tested that. When it comes to the maximum timing I will have to figure it out. But that is something I will look at after I come back after my vacations. Thank you too, Philipp Brogli

Hi everyone I'm pretty new to the entire FPGA developpment. I have a basic understanding of how VHDL works and I have managed to set up a blinking light with the current setup I have. But my project is a bit bigger than just blinking the onboard LEDs. The goal is to have three analogue inputs (read via Zmod Scope 1410-105s), one analogue output (Pmod DA3), do some signal processing and send the data to a computer. I found out how to use the Scopes. I have not yet connected it to a signal generator, but I have a general understanding on how to proceed. But when it comes to the signal output I'm a bit clueless. I think the ideal place to add the DAC is at the PMOD port A or when we look at the .xdc file it would be labeled Pmod Header JA. Is there an IP I can use or some sample project or do I have to program it myself from ground up? Thank you for your assistance.