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Problems on simulation using Zmod SCOPE ADC IP core in vivado




I am testing my code using Zmod SCOPE ADC  IP core named ZmodScopeController(1.2),I have alredy read the ZmodScopeController User Guide,and found that DCO clock is generated by ADC.So in the simulation,I provide a clock as DCO,also data as CHB DATA,then I run the simulation,found that the IP core does not work.It seems the sInitDoneADC signal always stays 0,same as sConfigError.The result is as below,here I invert the sInitDoneADCsignal as adc1410_init_done.The cDataAxisTdata[31:0] always stays 0,how can I figure it out and run the simulation?image.thumb.png.69078be87bb6b6afc090a3379ea30d7c.pngimage.png.460c2b3bdb26232792c3334e7cb6e4bb.png

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In January I finally could work on it for two full weeks instead of roughly half a day per week like before. Luckily I got the ADC to run as well as my own SPI port for the DAC. So could make a voltage follower where a picoscope compared the signal from the signal generator and the one going through the FPGA. It worked quite well and shouldn't be the Bottleneck in my future project.

My next step is making a webserver on the linux part of the FPGA. But for this part I have a coworker who knows how to do it and I can use some of his files for reference. So I hopefully don't need any help from the forum. The IP block of the ADC is still in his default settings though. If that causes any errors then I will have to spend some time playing around with them. 

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