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Hi all, I am an embedded software engineer trying to teach myself FPGA prototyping. I have been following the following tutorial "Getting Started with Vivado and Vitis for Baremetal Software Projects" https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi I am using the Nexys A7-100T board. I have followed the tutorial and validated the project, however when I go to implement the project I get critical timing errors. Below a few of the critical errors I get, and I have attached a screenshot of timing tab page. [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port btn_tri_io can not be placed on PACKAGE_PIN C12 because the PACKAGE_PIN is occupied by port reset. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["/home/user/codeDepot/digilentTutorialBareMetalSW/digilentTutorialBareMetalSW.srcs/constrs_1/imports/user/Nexys-A7-100T-Master.xdc":74] [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port btn_tri_io can not be placed on PACKAGE_PIN C12 because the PACKAGE_PIN is occupied by port reset. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["/home/user/codeDepot/digilentTutorialBareMetalSW/digilentTutorialBareMetalSW.srcs/constrs_1/imports/user/Nexys-A7-100T-Master.xdc":74] The tutorial is a great tutorial and does reference errors that may occur in some steps, however there is no reference to this error and what to do. I guess I have to modify some clock settings. Any help would be appreciated. Kind regards, Rochus
Good Morning Folks! And it is indeed morning, it has been a long day, I started this journey yesterday morning. By way of introduction, and to set an expectation of my level of understanding, I'm an embedded software engineer just dipping a toe in the waters of FPGAs. So very new to this! After a few weeks of playing around with the Verilog and RTL I'm now interested in Microblaze and following (faithfully or perhaps more accurately blindly) the guidance in https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi Sadly, things have not gone as smoothly as I had hoped. Despite sticking closely to the guidance I keep ending up with the following warning, which ultimately leads to a routing error: [DRC AVAL-46] v7v8_mmcm_fvco_rule1: The current computed target frequency, FVCO, is out of range for cell processor_i/mig_7series_0/u_processor_mig_7series_0_2_mig/u_ddr2_infrastructure/gen_ui_extra_clocks.mmcm_i. The computed FVCO is 562.500 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 15.000, CLKIN1_PERIOD = 26.66667, and DIVCLK_DIVIDE = 1 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)). I'm using a Nexys 7-100T so substituting DDR2 where the guide refers to DDR3, otherwise it is all pretty much identical. I have the constraints file is in place and the vivado board file is also correct. The system clock is correctly named and uncommented. This is, of course, all generated by the various automated connection and block assistants, I barely had to do anything manually. Having researched this there are a fair number of reports of this but mostly seem to be related to older versions of Vivado or people not setting up Clocking Wizards correctly. The tutorial doesn't use a Clocking Wizard, instead relying on timing from the MIG IP and I'm using the current version of Vivado. I can see where these values are defined in the generated IP constraint files but I really don't think I should be in there changing stuff to make this work. One thing I have noted is that the MIG clock period is defaulted to 3333ps (approx 300MHz), I seem to recall that the reference guide for the board says 350MHz for DDR2 but the IP configurator won't let me go higher than the 300MHz, in any case the tutorial doesn't ask me to manually change anything so I've let that be what it is. Any pointers (in English rather than FPGAish) would be greatly appreciated. As for me, I'm going to bed and will face this again in the morning :-) Cheers, Y.
Hello, I found a lot of open source and tutorials on how to build a 4 digit 7 segment display on the Nexys A7 board (or Nexys 4DDR). I was wondering how can I make all 8 digital displays light up and display a message in hexadecimals (ex: "85ECA921"). I'm doing this in xlinx vivado in VHDL code. I'll have attached of something that works for 4 digits, but can someone show me how to implement/ change the code to make all 8 digital displays work in that example I provided? Thanks serializer.xpr tb_serializer.vhd serializer.vhd my_genpulse.vhd hex2sevenseg.vhd serializer.xdc