thinkthinkthink
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Posts posted by thinkthinkthink
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This is the branch where the petalinux project for zybo z7-10 was moved: 10/Petalinux/upgrade.
And this should be the branch with the hardware for that petalinux project: 10/Petalinux/update.
Edit: The projects I linked where upgraded to 2021.1.
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Apparently you can get weird errors if you're running petalinux on an external HDD/SSD.
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Means this that is not compatible with the Genesys ZU? Is there a way to have such a connector for the Genesys ZU?
The FMC Pcam Adapter is not compatible with any UltraScale+ FPGAs, so any board that has such an FPGA not just the Genesys-ZU variants.
And yes, any MIPI camera should work.
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Are you running petalinux on a virtual machine or natively ? Anyway, make sure you have 8 or more gigs of RAM available and also check the log files that are mentioned in the errors.
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If you're using the TMP2 Pmod then you only need the MicroBlaze processor, the MIG7 IP and an IIC IP to write to and read from the adt7420. It says in it's datasheet that it has a 16-bit ADC so there's no need to use the XADC.
Also make sure to give the TMP2'S Reference Manual a read through.
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The Eclypse Z7 and the ZedBoard can do LVDS_25 but only on pins that are routed to the SYZYGY connectors (on the Eclypse) and to the FMC LPC connector (on the ZedBoard) which would mean you'd need a custom SYZYGY pod or FMC module to access those pins.
The only boards with a PMOD port connected to a FPGA bank supplied by an adjustable voltage source are the Genesys ZU variants.
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12 hours ago, filipj said:
Hello,
@thinkthinkthink is the hardware project for Zybo-Z7-20/Petalinux/upgrade published anywhere ?
Anyway, it seems that the license for mipi_csi2_rx_subsystem_0 IP is shipped for free in newer Vivado releases, so it would be great if https://github.com/Digilent/Zybo-Z7-20-base-linux could be updated to newer Vivado.
@canisio I presume you have retrieved the block diagram from .xsa ? Wouldn't you mind sharing hints how to do that ?
Here's the HW branch: Zybo-Z7-HW/20/Petalinux/upgrade. Were you not able to find it ? Should I let others know that this new repo structure is a bit confusing ?
And about that base linux project, it's obsolete but it was replaced by the project I just linked. I think it's the same project even, it's just that it was moved to a new repo.
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The JA pins are on Bank 34 which is supplied from VCC3V3 (page 8 of the Cora Z7 schematic) so no way you could do 2.5 V.
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If you just want to test the HDMI port you can move the jumper to QSPI for the board to boot from the Flash memory which contains an OOB demo project (also available on our github) that should exercise all available hardware on your board. If you connect the HDMI TX port to a monitor you should see something on that monitor.
Also @JColvin, there's already a 2021.1 Petalinux build for the Zybo Z7-20 here on this github branch. It's way more up to date than what you linked.
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You have to look in the design HDL wrapper file for the correct name of the pins, that's probably why manually mapping them did not work.
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That's why there's a README. But you can find how to recreate the xpr project from its sources by reading this guide: Digilent FPGA Demo Git Repositories. That guide also has instructions on how to recreate the Vitis project as well. Good luck.
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No, this is the most recent release of that demo project: the HW (Vivado) branch and the SW (Vitis) branch. We now use a new repo structure and update them there annually.
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You'll need to add our https://github.com/Digilent/vivado-library as an IP Repository in Vivado for that to work. I don't think connecting the Pmod ports directly to a Gpio IP from the Board Flow GUI will work since Vivado considers them different Interfaces (Pmod vs Gpio), so yeah you'll have to manually map the Gpio pins to a Pmod connector in the XDC file if you only want basic input/output.
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11 hours ago, canisio said:
They were upgraded 4 months ago. Checkout this branch: Zybo-Z7-20/Petalinux/upgrade.
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Have you tried other serial terminals like TeraTerm or Putty ?
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You probably need more pipelining to get rid of the weird VGA artifacts.
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I can't know for sure if the switches are broken, that's why you gotta find that out by testing them in your design. But yeah, the LED should be on if the value you read on the input of your gpio is '1'.
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But your and gate does not take into consideration the a and b inputs which come from the switches... So no matter what you do to those switches your output will always be the same. y should be equal to a AND b.
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Everything looks good, maybe do some debugging in vivado with an ILA, look at the output of your RTL module. Also, have you simulated it ? Does it work correctly ? It could also be that there's some issues with the physical switches on your board.
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How does your constraints file look like ?
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Oh I think I know what your problem is, on ZYNQ boards the USB/serial IC is hardwired to the ZYNQ processing system, so I don't think you can do something about it. You'll have to instantiate the zynq PS in your block design if you want serial communication via USB. Or you can pass the data from the uartps inside the zynq ps to your uartlite and then send it forward elsewhere.
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Make sure stdin and stdout are set to your axi uartlite ip in the BSP settings of your hardware platform.
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We've got a new series of tutorials on our youtube page, check them out.
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Why are you using that old guide and where did you even find it ? Here's the newer guide: Installing Vivado, Vitis, and Digilent Board Files. Also, which version of Vivado did you install, 2021.1 or 2021.2 ?
Genesys zu 5EV - Errors on Getting Started with Vivado and Vitis for Baremetal Software Projects
in FPGA
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You should follow this Genesys-ZU Hello World Demo Project Guide to get a better idea on how to work with our Genesys-ZU variants before trying anything else.