[Installing ZedBoard (Zynq7000) board files under Xilinx Vivado 2021.1]

You're supposed to choose RTL project with the "Do not specify sources at this time" checked. That's the default option and the best for beginners.

[Installing ZedBoard (Zynq7000) board files under Xilinx Vivado 2021.1]

Hey hey hey, we actually do upgrades of old demo projects. We'd done that last year and we've done it again this year. Check the <board_version>/<DEMO>/update branches of some of our github repos. As for the Vitis development for the Zedboard, the only issues I had last year with upgrading the Zedboard FMC-Pcam-Adapter demo from Xilinx SDK 2019.1 to Vitis 2020.1 were some makefile errors that I solved easily with a search through xilinx's forums where I found the solution which required modifying some makefiles. Now upgrading this Zed project from 2020.1 to 2021.1 should be pretty straightforward as it's all just Vitis.

[ov7670 programming based on Digilent Nexys3]

There is a much better guide out there: this one made by Lauri Võsandi.

I've got it working on the old Digilent ZYBO board (the non Z7 version that had a VGA connector).

Maybe you can get it working somehow. Good luck, you'll need it.

[Unable to generate bitstream file for Nexys A7 50T board usign vivado]

Can't help you with platformio but here's a guide on how to get our GPIO demo up and running on the Nexys A7: GPIO Demo Guide.

Also make sure to check out your board's Resource Center and its Reference Manual.

To install board files this guide, while a bit old, should work on all recent versions of Vivado. It's basically a tcl script that Vivado automatically runs at startup.

[Basys 3 speed?]

The product store page has a Features tab that is always worth checking out, the first line should always tell exactly which FPGA part is loaded on the board. Something along the lines of "Features the Xilinx Artix-7 FPGA: XC7A35T-1CPG236C" where XC7A35T is the part number, -1 is the speed grade and CPG236 is the package, the last C at the end probably tells you that it's a commercial grade fpga.

The Basys 3 Reference Manual should provide even more info than the store page. Seeing that you claim to be new to all this make sure to at least skim through it and consult parts of it later when needed. The schematic files can also be really useful in understanding what board you're working with.

[Using Genesys Zu as a blank FPGA]

Just change the boot jumper to JTAG and program the board with Vivado/Vitis. But I think you can just program the board even with linux running, it will download a new bitstream and overwrite anything else on the fpga.

[A strange problem when Programing FPGA using SDK]

Go to Debug Configurations...

 

Make sure that your application is selected there on the left, if there's no application you can make one using the button the leftmost arrow points to. Then go to Target Setup and press the Search... button next to the Bitstream File field.

You should get a prompt from which you can select the only available bit files.

Hope this helps.

[Nexys 100T Blinky tutorial error generating Bitstream]

3 hours ago, JB_ said:

I have the same problem, same board - Nexys7 100T.

Here's the constraint file, omitting comments and empty lines:

set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK }];
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED }]; #IO_L18P_T2_A24_15 Sch=led[0]

This is the error I get:

[Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports CLK]'. ["C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc":8]
[Common 17-55] 'set_property' expects at least one object. ["C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc":29]

A little more info is found in the synthesis report:

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc]
WARNING: [Vivado 12-584] No ports matched 'CLK'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:7]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:7]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'CLK'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:8]
CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports CLK]'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:8]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-584] No ports matched 'LED'. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:29]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/XXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc:29]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [C:/UsersXXXX/Documents/blinky/blinky.srcs/constrs_1/imports/digilent-xdc-master/Nexys-A7-100T-Master.xdc]
Completed Processing XDC Constraints

I'm following the instructions at https://reference.digilentinc.com/vivado/getting_started/start

I don't think they're complete, something is missing.  (I know absolutely nothing about this... which is why I bought the board, to get started with at least a blinking LED and a working flow.)

XDC constraints are case sensitive, so be careful with that.

[Can't get clocking to work for Arty + DDR3]

3 hours ago, apullin said:

Well, I also tried installing 2020.1 and reproducing the project, and I cannot get it to work.

With clk_ref_i = 200 Mhz , sys_clk_i = 100 Mhz, the error now reports CLICK1_PERIOD of 20.00000 . No idea what is going on.
 

That's because the recommended sys_clk_i frequency should be 166.667 MHz according to the Arty A7 Reference Manual and not 100 MHz.

[Can't get clocking to work for Arty + DDR3]

What version of vivado are you using cuz I've managed to generate a bitstream for the Arty A7-35T with no issues on Vivado 2020.1. Unfortunately, I don't have this board on me to test my configuration but the fact that the bitstream was generated without errors means it has a high chance of working.

Also, make sure the Clock Period is set to 3000 ps and that Input Clock Period is set to 6000 ps inside the MIG settings.

[executables selected for download on to the following processors doesn't exist or incorrectly specified. Do you wish to ignore them and proceed? 1.ps7_cortex9_0]

I think you weren't paying attention because the guy in the tutorial also gets that warning message but he just presses the Proceed button and ignores it.

It probably has something to do with the debug configuration when launched for the first time.

[Removing debug logic of pcam-5c reference design]

6 hours ago, Kyle_ISL said:

 

Hello,

I'm using zybo z7-20,  Pcam 5c with vivado 2019.1 for Zybo Z7 -20 Pcam 5C Demo 2019.1 release. I followed all the steps in https://github.com/Digilent/Zybo-Z7-20-pcam-5c?_ga=2.30634943.1211223159.1605501220-381318644.1601993729.

The program runs with no error, but I can't get the any image on the screen or the menu on the terminal. 

The video shows my monitor while I'm following demo instruction step. Plz let me the reason why it is not working.

 

Sorry but I couldn't replicate you problems, it worked first try for me following the exact same steps as you did.

 

But I can recommend some things you can try to hopefully get the project working properly. 

First you can try resetting the output products by right-clicking the block design file and then clicking "Reset Output Products...".

Then go to Tools -> Settings... -> IP, press the Clear Cache button and then click OK.

Now go to the Design Runs tab, right-click on impl_1 and select Reset Runs. Do the same thing for synth_1 as well.

After that click on Generate Bitstream and wait a bit for a new bitstream to be completed. If somehow you get some critical warnings telling you that the MIPI_D_PHY_RX_0 IP was packaged with a different board_part you can just ignore those by pressing OK and then clicking on Generate Bitstream again.

Now you should export the new hardware handoff and launch the SDK again (if the SDK is already open you don't have to launch it again).

Right-click on system_wrapper_hw_platform_0  and select Change Hardware Platform Specification to update it to the new hardware handoff.

After that you should clean the entire workspace and then build it all again.

Finally, you can program the FPGA and run the application again.

You will hopefully see something like this in your tera term console:

Please do let us know if you've encountered other problems or if, after following all these steps, you still couldn't manage to get the application working properly.