filipj

Hi @Niță Eduard, After substituting the xf_infra.hpp & recompilation of the IPs they work ! Thank you, I should have taken a look at known issues. I guess with this we can call Embedded Vision Workshop at least initially compatible with Vitis Vision 2020.1 library, will surely make some further experiments. One important thing to note is to remember to remove xf::cv:: from before ap_axiu, otherwise Vitis HLS will keep taking the struct definition from the wrong file. I was able to get both edge_detection and axi passthrough IPs to work (however when I connect both outputs of the edge_detect IP it stops to work for some reason). Thanks again, Filip

Hmm... after some more digging I've found out that the "stream" axi interface for freshly compiled IPs seems to be different than of the ones compiled with 2018. Presuming some pragmas/settings in Vitis HLS synthesis need to be modified (or the Embedded Vision Workshop design needs to be adjusted).

Hello @Niță Eduard, I tried this, unfortunately without any effect :( Tried some other experiments though, in Vitis Libraries there is a simple example that rewrites data from input to output (Vitis_Libraries/vision/L1/examples/axiconv). I tried to make it work with Embeddedd Vision Workshop design. Unfortunately, this also had zero effect, screen remains black. Have spotted one thing though. As I was mentioning before, color_to_bw and invert were the pre-compiled with whatever Vivado HLS the Embedded Vision Workshop was created (2018 ?) and these work just fine. However, when I put any of the 2020.1 Vitis HLS compiled IPs, after Validate design I can see a "Critical Warning" being reported for freshly compiled ones. It complains that TDATA_NUM_BYTES in axiconv and edge_detect is different than in the rest of the design. I was trying to figure-out what this parameter is and how it works, without success yet... Any further pointers ? Thanks, Filip xf_axiconv_config.h xf_axiconv_accel.cpp

Hello @Niță Eduard I was trying to do exactly the same as the colleague @HOOKJANDRO. Not sure if he ever succeeded. I was able to compile edge_detect IP from your example with vitis_hls, also was able to recompile the whole design in vivado. However, when I run the platform, I am able to see the output from the 2 older (pre compiled, color_to_bw, invert) HLS IPs, but not from the the one freshly compiled (edge_detect). Screen remains black :( I am also using Vivado 2020.1. Any hints what to to debug ? How to find out what is missing ? Regards, Filip P.S. I have commented out #pragma HLS INTERFACE ap_ctrl_none port=return in order to get the ap_start port, but the IP does not pump output to HDMI regardless of whether it is commented out or not.

I have just rebuilt the whole HW project and then petalinux project with updated HW bitstream (I used both projects from before update to 2021.1 because I use 2020.1) Up & running ! Great job! ?This gives plenty of opportunities. @thinkthinkthink you should really make this project more visible in your guides and on the forum. (I have found other threads where people were asking for updating this project). (Only issue I had was that in order to generate new bitstream successfully I needed to add manually constraint file to the Vivado project for some reason)

@thinkthinkthink Thanks, that's great ! I will check how it works in a minute. From commits I presume it is compatible with Vivado 2020.1 and 2021.1 ? Yes, the repo structure and READMEs are a bit misleading. Also, could page with demos point to the most recent repos ? This page is the resource I usually use to learn how to use Zybo, but it looks like there might be more examples that were not listed. https://digilent.com/reference/programmable-logic/zybo-z7/demos/petalinux?redirect=1 Most links and directions still point to the old repos where mipi IP wasn't for free. Also, it would be nice if this new repo could have "Releases" for each supported Vivado, same as the old one had.

Hello, @thinkthinkthink is the hardware project for Zybo-Z7-20/Petalinux/upgrade published anywhere ? Anyway, it seems that the license for mipi_csi2_rx_subsystem_0 IP is shipped for free in newer Vivado releases, so it would be great if https://github.com/Digilent/Zybo-Z7-20-base-linux could be updated to newer Vivado. @canisio I presume you have retrieved the block diagram from .xsa ? Wouldn't you mind sharing hints how to do that ?