Zybo demo projects in Vivado 2017.1

[mehdiru]

Hi,

I'm currently converting the Zybo demos to 2017.1. I already successfully completed several such conversions.

If anybody is interested, then I can share.

It would be great if this got published on Digilent's github ;-)

[hongquan18196]

Hi jpeyron,

I am using HDMI project to test my IP written by Vivado hls. But when I add my IP into HDMI project, it only show pattern. I think I have to control  AXILite bus for my IP but I don't know how do that.

Could you please have any idea for my proplem?

Thank you.

Quan Nguyen 

[hongquan18196]

Hi jpeyron,

Thank you for your support. I didn't use Tera term and I used a terminal in SDK. But I changed and It alway runs success. 

Thank you.

Quan Nguyen

[jpeyron]

Hi @hongquan18196,

I would suggest to add the ILA to your block design which will allow you to better trouble shoot issue. Have you looked into simulating your block design?

thank you,

Jon

[chrislafave]

Since I spent around two hundred bucks on my Zybo I'd like to be able to use the demos. Changing some version numbers inside a couple tcl files (...bd/system.tcl and ...proj/create_proj.tcl) still leads to another version-induced problem. It appears that Digilent no longer cares about new customers who use Vivado 2017.1 and beyond. Instead of learning I'm spending my free time trying to get your demos to work with Vivado 2017.1. 

Someone please tell me how to get the demos up to date.

Btw, the latest errors (for the "hdmi_in" demo) are this kind of doo-doo:

ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:ip:axi_vdma:6.2 
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
"create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_vdma_0 "
    (procedure "create_root_design" line 73)
    invoked from within
"create_root_design """
    (file "../src/bd/system.tcl" line 1669)

    while executing
"source $origin_dir/src/bd/system.tcl"
    (file "./create_project.tcl" line 102)

[chrislafave]

I just now achieved success with the dma_audio demo. I changed the "set scripts_vivado_version 2016.4" to 2017.1 in line 23 of system.tcl and changed the "Vivado Synthesis 2014" to 2017 in lines 72,75,88,91 of create_project.tcl. I'd also taken the advice, 'Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script.' in line 28 of system.tcl. I'd erased the project and run the create_project.tcl each time I tried something new until it worked.

Unfortunately, this same procedure didn't fully work on the hdmi_out demo. It errored before it got to wiring the blocks together:

ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source: 
/axi_dynclk_0/REF_CLK_I
/axi_dynclk_0/s00_axi_aclk
/axi_gpio_btn/s_axi_aclk
/axi_gpio_hdmi/s_axi_aclk
/axi_gpio_led/s_axi_aclk
/axi_gpio_sw/s_axi_aclk
/axi_mem_intercon/ACLK
/axi_mem_intercon/S00_ACLK
/axi_mem_intercon/M00_ACLK

ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design /home/chris/digilent_git_zybo/Projects/hdmi_out/proj/hdmi_out.srcs/sources_1/bd/hdmi_out/hdmi_out.bd 
ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.

    while executing
"make_wrapper -files [get_files $design_name.bd] -top -force"
    invoked from within
"add_files -norecurse [make_wrapper -files [get_files $design_name.bd] -top -force]"
    (file "./create_project.tcl" line 110)
update_compile_order -fileset sources_1

[jpeyron]

Hi @chrislafave,

Here is a forum that has the process to get the Zybo projects working in the new versions of Vivado. In the thread I am doing it for Vivado 2017.2 but you just need to use 2017.1 instead. So far I have not had any issues with this process. Let me know I you are not able to get the project working.

cheers,

Jon

[JColvin]

Hi @mehdiru,

I know a number of people that would be interested in such a conversion! I personally think it would be great if we incorporated your work on our GitHub, but unfortunately I don't have control over such things. I did let our content manager for our GitHub know what you have done though and that you would like to share your work, so hopefully that all goes smoothly.

Thanks,
JColvin

[chrislafave]

Thank you very much for that. I followed that post, having fixed the tcl files and updated the IP's with "report IP status". There is no "hdmi_out_bd.tcl" in .../hdmi_out/hw_handoff (as mentioned in the post), only hdmi_out_wrapper.hdf. Unfortunately adding a wrapper stopped at:

make_wrapper -files [get_files /home/chris/digilent_git_zybo/Projects/hdmi_out/proj/hdmi_out.srcs/sources_1/bd/hdmi_out/hdmi_out.bd] -top
ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source: 
/axi_dynclk_0/REF_CLK_I
/axi_dynclk_0/s00_axi_aclk
/axi_gpio_btn/s_axi_aclk
/axi_gpio_hdmi/s_axi_aclk
/axi_gpio_led/s_axi_aclk
/axi_gpio_sw/s_axi_aclk
/axi_mem_intercon/ACLK
/axi_mem_intercon/S00_ACLK
/axi_mem_intercon/M00_ACLK

ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design /home/chris/digilent_git_zybo/Projects/hdmi_out/proj/hdmi_out.srcs/sources_1/bd/hdmi_out/hdmi_out.bd 
ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.

[jpeyron]

Hi @chrislafave,

Are using our original Zybo HDMI-OUT project here made in Vivado 2015.4? The tcl script is here: hdmi_out/src/bd/system.tcl? I just completed bitstream on the zybo hdmi-out project in Vivado 2017.1. I would suggest to used a project that you have not made changes to or opened with vivado yet. Make sure you are using the Vivado 2016.4 version of the Zybo HDMO-OUT here. Make sure that you have downloaded and added the contents of the vivado library from here in the repo\vivado-library folder here:   Zybo-hdmi-out-master\repo\vivado-library. Then edit the hdmi_out_bd.tcl from 2016.4 to 2017.1 here:  Zybo-hdmi-out-master\src\bd\hdmi_out\hw_handoff. After editing load the project in Vivado 2017.1 , upgrade the IP cores by going to tools->reports-> report ip status. Next create a wrapper and then generate a bitstream. 

cheers,

Jon

[chrislafave]

I ran "Show IP Status" in order to find out that I can't upgrade the "locked IP's". As you can see in the screenshot, the "Upgrade Selected" button is grayed out.

ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'hdmi_out.bd' is locked. Locked reason(s):
* BD design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
List of locked IPs: 
hdmi_out_auto_pc_0
hdmi_out_s00_regslice_0
hdmi_out_xlconstant_1_0
hdmi_out_axi_mem_intercon_0
...
hdmi_out_processing_system7_0_axi_periph_0
hdmi_out_processing_system7_0_0
hdmi_out_xlconstant_0_0

ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.
 

[chrislafave]

Booyah! I ran "upgrade_ip [get_ips *]" and it upgraded them all! Saved by the command line again!  

Thanks again, jpeyron!

[jpeyron]

Hi @chrislafave,

Glad to hear you were able to get the IP's to upgrade.

cheers,

Jon

[hongquan18196]

Hi all,

I ran HMDI_IN project(2015.4) in vivado 2016.2 which got from "https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start".  I have the error:

ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source: 
/dvi2rgb_0/TMDS_Clk_p
/dvi2rgb_0/TMDS_Clk_n

ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design F:/LVTN/HDMI/Zybo-hdmi-in/src/bd/hdmi_in/hdmi_in.bd 
ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.

Please help me fix it.

Thank you,

Quan Nguyen

[hongquan18196]

Hi @jpeyron

Could you have any example related the ILA? I never work with ILA.

Thank you so much,

Quan Nguyen

 

[jpeyron]

Hi @hongquan18196,

After adding the ILA IP Core in the block design right click on the ILA IP Core and select open IP example design. Here are some xilinx documentation for the ILA that should be helpful as well.

cheers,

Jon

[JColvin]

Hi @hongquan18196,

We responded to your other post here.

Thanks,
JColvin

[hongquan18196]

Hi JColvin,

Thank you for your comment. I ran the demo project successfully.

Regards,

Quan Nguyen

[JColvin]

Letting you know that I'm also still waiting for how we would like to incorporate this work that you have done. Offhand I would recommend sending a pull request, but I personally don't know if that is the way we would like things structured since I imagine there is a chance we would want different folders for different versions of Vivado on GitHub, but again I'm not sure on that.

Thanks,
JColvin

[jpeyron]

Hi @hongquan18196,

Glad to hear you were able to get the demo going.

cheers,

Jon

 

[jpeyron]

Hi @blanca12,

We are in the progress of upgrading most of our projects to Vivado 2018.2. The easiest way to upgrade the project is to open the project in the recommended Version of Vivado. Then close the project and open the same project in the newer version of vivado with selecting to upgrade. For most of the projects you can also load the project in the newer version of vivado, upgrade the ip cores, create a wrapper and then generate a bitstream. What specific demo are you having issues with for the Zybo.

Jon

 

[hongquan18196]

Hi jpeyron,

I ran the demo project successfully. But I run again, It does not stream through HDMI and just shows a pattern. when I control on UART, I press any button It alway shows "Invalid Selection" and  a input signal transmit and process very slow. I don't understand what is going on.

Could you make me clean this?

Thank you.

Quan Nguyen

[jpeyron]

Hi @hongquan18196,

If you are using Tera term make sure to left click on setup->terminal and select local echo so you can see what you are entering and in new line select transmit as CR+LF.  Are you following the  HDMI Display Options in the wiki demo page here. Please attach some screen shots of whats going on in the serial terminal.

thank you,

Jon