Jump to content

HDMI to VGA on Zybo


Recommended Posts


I am trying to develop a simple project for HDMI to RGB. I am using dvi2rgb core and clock_wizard for generating a reference clock for it. I supplied 200MHz to dvi2rgb. I tried both MMCM and PLL modes in clock_wizard configuration. But when I dump the bitstream on Zybo Vivado shows the following warnings and my design doesn't work.

WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.

1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].


 Attached are my block diagram which I'm implementing, and my constraints file.

Please help me. I have read a lot of posts on this project but couldn't find any solution that can work for me. If you want my project file I can attach it as well.




Link to comment
Share on other sites


Yeah, you can usually ignore that missing debug core warning.  I get it all the time because I never use any Vivado debug cores.  What it basically means is that Xilinx's Vivado toolsuite will be unable to debug your design.  For me, that's just fine--I do my own debugging.

If you want to have a debug core in your design, you'll have to connect one up from the Xilinx IP cores library.  I think this link might have within it a description of how to do that, although I haven't read it myself.


Link to comment
Share on other sites

Hi @Uzaif,

Here is our HDMI in to VGA out project made for Vivado 2016.4. you will also need to download the vivado library here and make sure the contents are in the vivado library folder in the repo folder of the project before using the tcl scrip to launch the project. Here is the tutorial for the Hdmi_in project. Hope this helps!





Link to comment
Share on other sites

  • 2 weeks later...
  • 3 weeks later...

hello i can not create a wrapped hdl i am new in fpga the error is:

ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'hdmi_in.bd' is locked. Locked reason(s):
* BD design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:

can you help me?


Link to comment
Share on other sites


This topic is now archived and is closed to further replies.

  • Create New...