Must ones use MRCC pin when sampling data to a clock?

[Korken]

Hi all,

I am implementing a simple parallel interface to an FT232H from FTDI to use the 60 MHz 8-bit parallel interface for training VHDL.
While doing this a question popped up that I was unable to find answer to, the FT232H delivers a sampling clock to which all signals are synchronous - when sampling signals to this clock does this clock have to be routed to an MRCC pin or not?
It seems that MRCC pins should be used for global clocks, but what about sampling clocks?

Thanks for any clarification!

[jpeyron]

Hi @Korken,

I will reach out to our design engineer and see if this is something we can respond to.  We typically do not answer questions that deal with our programming solutions. They are considered proprietary. In the mean time hopefully one of our more experience forum members might be willing to respond to your question.

cheers,

Jon 

[jpeyron]

Hi @Korken,

The response i got is as follows: Ideally it would go into an SRCC or MRCC pin. An SRCC is fine if you aren’t trying to clock the entire device (FPGA) off that input, which you shouldn’t be, since the clock doesn’t run continuously. On the Genesys 2 we routed the clock into an MRCC pin but that was out of convenience, not necessity.

 

cheers,

 

Jon

 

[Korken]

Thank you for the answer, then it is as I suspected.
I also noticed that you can force the tool to use a "normal" I/O for clock input by specifying that in the XDC, but it was generally not recommended.