AXI DMA test errors on Petalinux

[Antonio Rios]

Hi everyone,
I'm trying to use the axi_dma xilinx driver in order to make transfer between PS and PL in both way. I posted this issue on the xilinx forum but I didn't get any response.
This is the link: https://forums.xilinx.com/t5/Embedded-Development-Tools/AXI-DMA-test-err...

Now I'm using the version 2016.3 for both software, Vivado and Peralinux.

Any idea?? I have looked for across the web but I cannot be able to manage the axidma engine.
Thanks in advance
Best,

[sbobrowicz]

You imported your .hdf into the petalinux project, correct? This should make sure that the interrupt values and register addresses in pl.dtsi are correctly auto generated. I believe the interrupts values are supposed to be lower than 58 and 59... unless you are using a lot of interrupts they should be around ~30ish (sorry don't have exacts right now). 

The message you reported said:

xilinx-vdma 40400000.dma: Xilinx AXI VDMA Engine Driver Probed!!

Do you have an axi_vdma core in your vivado block diagram or an axi_dma core?

Also, what do you DMA channels go to? I'm not familiar with the xilinx dma test driver, are you supposed to loopback the dma channels in the block diagram?

[Antonio Rios]

Hi @sbobrowicz
 
Thanks for your reply. Yes, I imported my hdf into my petelinux proyect. Attached you can find my pl.dtsi file (pl.dtsi), where I have changed interrupt values according to the xilinx axi dma wiki page (http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs)

I have an axi_dma core in my vivado block design, where the dma channel are connected like a loopback. The message "xilinx-vdma 40400000.dma: Xilinx AXI VDMA Engine Driver Probed!! " appears because from the petalinux version 2016.3, all axi dma drivers are merger in the same driver. On the wiki (http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs), at the end of the page you can find a change log about that:

• Deleted the AXI DMA/CDMA driver and Merged the AXI DMA/CDMA code with the VDMA driver
• Merged all the 3 DMA's drivers into a single driver

I don't know if I'm loosing something in the petalinux configuration. I'm working on this issue from long time but I have no idea what I'm doing wrong.

Any idea?

Best,

[sbobrowicz]

Thanks for providing the pl.dtsi, that clears a few things up.

Can I see your system-top.dts? I'm assuming your using the preferred petalinux approach where customizations are made there. It should include your axi dma test node.

A screen grab of your block diagram wouldn't hurt either. What are you clocking the axi stream interfaces with?

I've never really used the xilinx dma test driver before, but I'll take a peak and see if I see anything.

[Antonio Rios]

Thanks for your response.

Attached you can find my system-top.dts file (system-top.dts). In this file I add the axi_dma_test node. Attached you can find a screen shot of my block diagram. The used clock (FCLK_CLK0) for my design is 50MHz and it is generated by the precessing system module.

The idea of using the axi dma test is to check that everything is well configure in order to use the xilinx driver for axi dma. Now I manage the axi dma module form the user space, writing and reading the control/status registers of the axi dma mapped on /dev/mem. This solution is fine for testing but now I need to use the real driver in order to make my solution more robust.

Best,

[sbobrowicz]

I'm sorry, nothing is really jumping out at me here. I am trying to find time to dig into xilinx's dma test driver, but honestly I don't think I'm going to be  able to get around to it. Maybe just try writing your own dma test driver, which can double as sort of an exercise to learn more about the dma subsystem. It sounds like you have the axi dma working from user space, so that suggests that you have a good start on understanding how it works.