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Found 19 results

  1. Hello everbody, I built petalinux 2021.2 for zybo z7-20, but I want to develop some opencv and QT project on petalinux so, I need see petalinux desktop environment. I plug in HDMI kable but I couldnt see anything on screen. How can I set up desktop environment zybo z7-20 petalinux.
  2. I need a urgent help regarding this, Please help me, I booted my board with 5V wall connector and when i connect micro usb to laptop com port is not detected, i tried with different laptops too still did not work. I have added USB 0 in my design and it seems petalinux booted just fine since i can see PGOOD and DONE LEDs are on and my counter is running. I even tried different cables install drivers manually, I can see my petalinux booted and as soon as i turn on my RX led blinks for some time and then stops and board LED and Switches works as i configured. But COM port is not detected. I Tried different PC as well. nothing works. Please let me know the solution. Please do help.
  3. Hello, We are trying to add the Cora Z7 as a custom board into Matlab to allow model based development. We have been following this guide: define-and-register-custom-board-and-reference-design-for-zynq-workflow, but are getting stuck at linking to the Linux bit (the last step); (step 4 of section 'Integrate the IP core with the Xilinx Vivado environment' referenced here Getting Started with Targeting Xilinx Zynq Platform). We have Petalinux installed on an SD card, and can ssh into this etc., but its missing the necessary matlab customisation. We need to either use build root, or customise the Petalinux build. From Mathworks: So my questions are: Does anyone have a built image for the Cora Z7 using either of these methods? / a Linux image that we can use for this board with Matlab?. Can we use buildroot with the Cora Z7, such as by using the Zybo as an example and adapting this to suit the Cora? HAs anyone tried this? Does anyone have experience of the drivers necessary for Matlab, and how to add these to and rebuild the Petalinux kernel source? Cheers, Sean.
  4. Hi! I am trying to create a petalinux project using microblaze on nexys4 DDR. I followed the tutorial in this link https://portfolium.org/entry/petalinux-for-microblaze . I used the board files for my board. Everything works fine, but I can't build the project. I get some errors that some files can't be found but I don't know why they are not generated because there is no warning or error when I create or configure the project. There are 49 of these errors when trying to build. I use petalinux 2017.4, vivado 2017.4 on ubuntu 16.04. Anyone can help me to solve this problem ?
  5. I created a petalinux project using the following commands and wanted to use my own Hardware Description File (.hdf) generated by IP Integration Demo. I have attached the Hardware Description files exported by vivado 2016.4. $petalinux-create --type project -s ./Petalinux-Zybo-Z7-20-2017.4-2.bsp --name hf2-petalinux $cd hf2-petalinux $petalinux-config --get-hw-description=/home/jeremy/workspace/vivadoProj/IpIntegrate/IpIntegrate.sdk/IpI_wrapper_hw_platform_0/ But I cann't build the petalinux project to generate images when I stepped to run `petalinux-build` command. The info prompted to the terminal is as follows: jeremy@j-XPS-8700:~/workspace/zybo-z7-20/hf2-petalinux$ petalinux-build --verbose [INFO] building project [INFO] sourcing bitbake INFO: bitbake petalinux-user-image Loading cache: 100% |#####################################################################| Time: 0:00:00 Loaded 3257 entries from dependency cache. Parsing recipes: 100% |###################################################################| Time: 0:00:01 Parsing of 2473 .bb files complete (2434 cached, 39 parsed). 3266 targets, 226 skipped, 0 masked, 0 errors. NOTE: Resolving any missing task queue dependencies Initialising tasks: 100% |################################################################| Time: 0:00:05 Checking sstate mirror object availability: 100% |########################################| Time: 0:00:01 NOTE: Executing SetScene Tasks NOTE: Executing RunQueue Tasks fsbl-2017.4+gitAUTOINC+77448ae629-r0 do_compile: NOTE: fsbl: compiling from external source tree /opt/pkg/petalinux/tools/hsm/data/embeddedsw ERROR: device-tree-generation-xilinx+gitAUTOINC+3c7407f6f8-r0 do_compile: Function failed: do_compile (log file is located at /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/temp/log.do_compile.14317) ERROR: Logfile of failure stored in: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/temp/log.do_compile.14317 Log data follows: | DEBUG: Executing shell function do_compile | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:77.1-14 Label or path axi_dynclk_0 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:82.1-12 Label or path axi_vdma_1 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:85.1-10 Label or path v_tc_out not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:91.1-9 Label or path v_tc_in not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:94.1-12 Label or path axi_vdma_0 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:97.1-16 Label or path axi_gpio_video not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:100.1-9 Label or path pwm_rgb not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:139.1-15 Label or path axi_i2s_adi_0 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:155.1-14 Label or path axi_gpio_led not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:160.1-17 Label or path axi_gpio_sw_btn not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:164.1-14 Label or path axi_gpio_eth not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:201.1-11 Label or path axi_iic_0 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:225.1-26 Label or path mipi_csi2_rx_subsystem_0 not found | Error: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/system-user.dtsi:264.1-15 Label or path v_frmbuf_wr_0 not found | FATAL ERROR: Syntax error parsing input tree | WARNING: /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/temp/run.do_compile.14317:1 exit 1 from 'dtc -I dts -O dtb -R 8 -p 0x1000 -i /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0 -i /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/../components/plnx_workspace/device-tree/device-tree-generation -o /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/../components/plnx_workspace/device-tree/device-tree-generation/plnx_arm-system.dtb /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/../components/plnx_workspace/device-tree/device-tree-generation/plnx_arm-system.pp' | ERROR: Function failed: do_compile (log file is located at /home/jeremy/workspace/zybo-z7-20/hf2-petalinux/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+3c7407f6f8-r0/temp/log.do_compile.14317) ERROR: Task (/opt/pkg/petalinux/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree-generation_git.bb:do_compile) failed with exit code '1' NOTE: Tasks Summary: Attempted 3295 tasks of which 3288 didn't need to be rerun and 1 failed. Summary: 1 task failed: /opt/pkg/petalinux/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree-generation_git.bb:do_compile Summary: There was 1 ERROR message shown, returning a non-zero exit code. ERROR: Failed to build project webtalk failed:PetaLinux statistics:extra lines detected:notsent_nofile! webtalk failed:Failed to get PetaLinux usage statistics! Does anyone have any work-around to the errors? Any points would be appreciated! PS: I have separately tested the application of IP Integration Demo to bare-metal (Zybo-z7-20) and petalinux project using default Hardware Description configuration. Kept all default options when running `petalinux-config -c u-boot`, `petalinux-config -c kernel`, and `petalinux-config -c rootfs`. Additionally, I have tried to split `petalinux-build` process by several detailed steps, i.e., running `petalinux-build -c bootloader`, `petalinux-build -c u-boot` and other following commands. The first one `petalinux-build -c bootloader` can be finished successfully. But when I execute `petalinux-build -c u-boot`, the errors similar to above prompt out. IpI_wrapper_hw_platform_0.tar.gz
  6. I am trying to use the PmodCAN module together with PetaLinux on the ZedBoard, to display a CAN interface within the OS. So far I can make it show up in the interface overview with the following device tree overlay: /* <petalinux-project-root>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi */ /include/ "system-conf.dtsi" / { osc: can_osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <20000000>; }; }; &gpio0 { #interrupt-cells = <2>; interrupt-controller; }; &spi1 { is-decoded-cs = <0>; num-cs = <1>; status = "okay"; spidev@0x00 { compatible = "microchip,mcp25625"; spi-max-frequency = <10000000>; clocks = <&osc>; interrupt-parent = <&gpio0>; interrupts = <0 0x2>; reg = <0>; } }; I can even send and receive messages using `candump` and `cansend`, but the interface behaves strange together with some CAN libraries. E.g. Messages are sometimes not sent, when the library tries to send multiple messages without any delay between them. On the other hand, when I connect the PmodCAN to a RaspberryPi and use same said libraries, everything works fine. So the only difference I can see between the working Raspberry Pi and the "strange" behaving Zynq setup, is the manually defined device tree overlay you see above. Long story short: Is my device tree overlay for the PmodCAN correct, to use it together with the ZedBoard on the JE Pmod connector? Maybe there is even a template somewhere? Based on the issues I have, I suspect something might be wrong with the clock and frequency definitions ...
  7. Hello. Im trying to read an I2C sensor (ADXL357) with a Zybo Z7-10. Im kinda lost since im not an expert on fpgas. Im using this design on vivado 2019.2 ##Clock signal set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }]; ##Pmod Header JC set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { port_i2c_scl_io }]; #IO_L10P_T1_34 Sch=jc_p[1] set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { port_i2c_sda_io }]; #IO_L10N_T1_34 Sch=jc_n[1] ls /dev gives only i2c-0 interface. Im working with a pynq framework that uses petalinux as base. For now im not using python but im trying first to detect the sensor address (from linux) and then do the logic (python or with sdk) When i connect to the Pin 1 and 2 of the PMOD JC i dont detect nothing with "sudo i2c -r -y 0" only "--" on all the addresses. I have tried other ports but no response yet. What am i doing wrong? Is Pin 1/2 correct on JC? i dont understand why linux doesn't detect the sensor. The reference manual says that any pin can be routed throug PMOD but how do i said to the linux that P1-2 of JC is the i2c? (i have all pmods available so i can use all). Thanks EDIT: cat ./petalinux_project/build/tmp/work-shared/plnx-zynq7/kernel-source/arch/arm/boot/dts/zynq-7000.dtsi amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; ... ... i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; Is I2C disabled right? what should be the device tree to enable the pins on a pmod? modifying the dts then i should recompile boot.bind and image.ub and replace it on the sd?
  8. Hello, Does ZedBoard 4PCam FMC Adapter Demo Design support Petalinux? Regards,
  9. Hello, I am working with ZedBoard. I have created a custom IP using Vivado for my project. I have tested the working of my custom IP by setting the registers using "Xil_Out32 function (Xilinx SDK baremetal application)" . I have also stored output data of my custom IP to text file on the SD card (using xilffs). Now my objective is to create a petalinux project and implement similar functions(how I have used in baremetal). I dont know how to use Xil_out and xilffs library functions in petalinux. According to my understanding these are specifiaclly used in baremetal application. (in Xilinx SDK). It would be great for me if someone guide me for creating petalinux project application my project. Thanks and regards
  10. Hello everybody, I am working on Image processing pipeline using zybo and Pcam. I have reference hardware design and petalinux project from v2017.4 by Digilent Hardware Design : https://github.com/Digilent/Zybo-Z7-20-base-linux Petalinux project : https://github.com/Digilent/Petalinux-Zybo-Z7-20 I have tested this project in v2017.4 and it works perfectly well. I am trying recreate it using only Xilinx IP cores and xilinx linux kernel. I notice that the petalinux project uses Digilent's kernel for drivers and not the xilinx kernel. Also another difference in the design is that I do not have the display part included in the design as I only need the images to be captured and not displayed. The pipeline is as follows Sensor--> MIPI CSI2 Rx Subsystem -> Video Frame Buffer --> PS I am able to get the media graph ans also set it to the format and resolution that I want. However after that when I use yavta application to save the Images it freezes (Please see the images below) Is there any differences in the kernel that is causing this issue. Any help is higly appreciated.
  11. I am looking at the petalnux demo here https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/demos/petalinux and https://github.com/Digilent/Petalinux-Zybo-Z7-10. These are a good resource. I am anxiously awaiting the update to 2020.1. However, I would can you include or provide here a list of the steps need to recreate the functionality in the distributed BSP. You don't need to provide in depth instructions as we can reference the provided petalinux project. For instance, I don't even know where to start looking for how to configure the HDMI video driver on a new project. With a list of steps on how to recreate the project from scratch it will be a better learning tool. thanks!
  12. Can someone show me how to enable a GUI for the petalinux project available here: https://github.com/Digilent/Petalinux-Zybo-Z7-10 I changed it to have an external rootfs on the SD card and activated the matchbox desktop session in the rootfs configuration, but when it boots I get the following error: # matchbox-desktop ** (matchbox-desktop:1242): WARNING **: Cannot open display: Not sure how to get the HDMI display working...
  13. Hello Digilent team, I was able to integrate the bare metal HDMI out on Arty-Z7-20 thanks to your demo from here: https://github.com/Digilent/Arty-Z7-20-hdmi-out/tree/v2020.1 I wonder if you have any plan to make a petalinux version for it with HDMI output integrated on Xilinx toolchain v2020.1? If not yet, do you know where can I start? I don't see documents from Xilinx developing from scratch like this. I found a similar post here but for v2017.v: Looking forward for your advices. Thanks and best regards,
  14. Hello sir We purchased "Arty-Z7-20" a few weeks ago. We are trying to boot a project using the petalinux. We have followed the manual given in the below links. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug1144-petalinux-tools-reference-guide.pdf https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1157-petalinux-tools-command-line-guide.pdf But the Arty-Z7-20 board didn't get booted via jtag or SD card. We have also followed steps provided on belowed github, but it won't work.. https://github.com/Digilent/Petalinux-Arty-Z7-20 Output while running boot command shown below, '$ petalinux-boot --jtag --prebuilt 3 --hw_server-url TCP:127.0.0.1:3121' INFO: Sourcing build tools WARNING: Will not program bitstream on the target. If you want to program bitstream, WARNING: please run petalinux-package --prebuilt to put the bitstream to the prebuilt directory, WARNING: or use --fpga --bitstream option to specify a bitstream. INFO: Append dtb - /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/system.dtb and other options to boot zImage INFO: Launching XSDB for file download and boot. INFO: This may take a few minutes, depending on the size of your image. rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device INFO: Downloading ELF file: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/zynq_fsbl.elf to the target. INFO: Downloading ELF file: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/u-boot.elf to the target. INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/system.dtb at 0x00100000 INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/uImage at 0x00200000 INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/rootfs.cpio.gz.u-boot at 0x04000000 INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/boot.scr at 0x03000000 INFO: SOC Silicon version is 3.1.
  15. Hello, Can you say me why zybo didnot update the bsp version of zyboz7 board ? I see that they have only 2017 version . My petalinux version is 2018.3 and vivado is 2018.3 . So it giving me error failed to generate the rootfs while building project in the petalinux . It also says that No such file or directory. I search many forums and find that this is the problem with the bsp version. Does anyone know how use the 2017 zybo bsp with higher version of petalinux ? I used this commads petalinux-create -t project -s /home/kawser/PetaLInux/zybo.bsp petalinux-config --get-hw-description /home/kawser/PetaLInux/ petalinuxb-build
  16. Hi, I'm trying to boot petalinux from TFTP server and NFS root based on Arty Z7-20 Petalinux BSP Project (https://github.com/Digilent/Petalinux-Arty-Z7-20) Unfortunately, TFTP boot method is not included in the Project's README.md file. I found several useful infromation and tried them to my Arty-z7-20 board. [1] TFTP Boot and NFS Root Filesystems : https://elinux.org/TFTP_Boot_and_NFS_Root_Filesystems [2] Petalinux with Root NFS and Kernel on TFTP sever : https://www.youtube.com/watch?v=DHmcjkDDAlM [3] running netboot with u-boot-xlnx : https://forums.xilinx.com/t5/Embedded-Linux/running-netboot-with-u-boot-xlnx/td-p/760236 It was passed to access TFTP server on HOST PC (Ubuntu 18.04). However, I failed to access NFS Root Filesystems on Host PC. These were Host-PC settings netplan Static IP : 23.44.127.35/24 gateway4 : 24.44.127.1 /etc/exports /srv/nfsroot 23.44.127.1(rw, sync, no_root_squash, no_subtree_check) TFTP server directory : /var/lib/tftpboot files : BOOT.BIN, image.ub, zynq_fsbl.elf etc... settings (/etc/default/tftpd-hpa) TFTP_USERNAME="tftp" TFTP_DIRECTORY="/var/lib/tftpboot" TFTP_ADDRESS=":69" TFTP_OPTIONS="--secure" NFS Root directory : /srv/nfsroot files : root files extracted from rootfs.tar.gz And, these were Petalinux settings Ethernet Settings Static IP address : 23.44.127.1 Static IP netmask : 255.255.255.0 Static IP gateway : 23.44.127.1 Image Packaing Configuration Location of NFS root directory : /srv/nfsroot NFS Server IP address : 23.44.127.35 tftpboot directory : /var/lib/tftpboot I started TFTP and NFS servers on Host-PC $ sudo service tftpd-hpa restart $ sudo service nfs-kernel-server restart After copying BOOT.BIN file to SD-card and inserting it to Arty-z7-20 board, I powered up the board and checked the status of server on Host-PC Zynq> ping 23.44.127.35 Using ethernet@e000b000 device host 23.44.127.35 is alive Downloading "image.ub" file from TFTP sever is successful. Zynq> tftpboot image.ub Using ethernet@000b000 device TFTP from server 23.44.127.35; out IP address is 23.44.127.1 Filename 'image.ub'. Load address: 0x10000000 Loading: ########################################## ########################################## 9 MiB/s done Bytes transferred = 3779188 (39aa74 hex) I started netboot and got kernel panic error Zynq> run netboot ... ALSA device list: No soundcards found. VFS: Cannot open root device "(null)" or unknown-block(0, 0): error -6 Please append a correct "root=" boot options; here are the available partitions: ... ---[end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)... This is expected correct message from ref. [2] Could you help me find the problems? Thank you!
  17. I have generated the bit file from Vivado 18.2 which is installed in windows PC. Now I am trying to generate the SD card image boot file (.bin and .ub files) from petalinux 18.2 installed in a seperate linux PC. I have gone through the ug1144, but I am not able to figure out how to generate. Please share the point wise steps. its very urgent. Thanks in advance.
  18. Hello, I am currently working on a project using the Zedboard and some Pmods from Digilent. As of now, I have booted Ubuntu 16.04 onto the ARM core using the Petalinux tools through an SD card. I have also been looking into the GPS pmod and got the bare-metal example to work from programming the FGPA. Through my personal computer (Ubuntu 18.04), I have been able to interface with the Ubuntu 16.04 on the ARM and the GPS pmod. However, I am a little confused as to how the GPS pmod in the PL communicates with the Ubuntu on the ARM. I would really appreciate some insight on the last leg of this triangle of communication. For the bare-metal exercise, I used the IP blocks provided in the vivado-library. I noticed that there were a few files under the driver folder that were related to the software side, but I'm unsure how to move forward. When I rebuilt the Petalinux package with the hdf that included my GPS pmod, the module did not show up on Ubuntu. Do I need to create the hardware driver separate from the vivado-library files? If yes, is that using the petalinux tools or SDK or something different? I have already looked into most of the forum posts and Xilinx documentation provided for the Zedboard, pmods, and petalinux, but did not find an explicit explanation. Thank you in advance!
  19. Hi, I've opened the Cora-Z7-10-base-linux project in Vivado 2017.4 (to avoid any version-dependent issues) on Linux, and I was hoping to be able to route the UART 1 device from the ZYNQ7 Processing System out to the outside world. Ideally I'd like it to be wired up to the DP0 and DP1 pins, as I have a nice little Arduino Click2 adapter that I can put an RS485 Click board one. However, being very new to all this Zynq/Cora/Vivado stuff, I'm not sure how to do it. I started off (with a bit of advice from someone who knows more about this than me, but was rushing off home!) by opening the ZYNQ7 Processing System for re-customisation, and, in the Peripheral I/O Pins view, clicking on the EMIO button at the end of the UART1 row, and clicking OK. At this point, the block design is updated and UART_1 shows up on the ZYNQ7 Processing System block. Then I expanded UART_1 and, for each of the signals, right clicked and selected "Make external" before saving the block design and doing "Generate Block Design" again. The signal names related to UART 1 then showed up in the wrapper VHDL. Next, to try to map then to the Arduino I/O pins, I edited the constraints file by uncommenting and updating the ck_io0 and ck_io1 lines to be as follows: set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { UART1_RX_0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0] set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { UART1_TX_0 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1] Save, and "Generate Bitstream" to make all the steps run.. Unfortunately it breaks here with the following errors and critical warnings in the Messages view: Implementation Design Initialization [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port UART1_RX_0 can not be placed on PACKAGE_PIN U14 because the PACKAGE_PIN is occupied by port shield_dp0_dp13_tri_io[0] ["/home/jmccabe/work/Cora-Z7-10/Cora-Z7-10-base-linux/src/constraints/Cora-Z7-10-Master.xdc":92] Place Design [Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 1 sites. Term: UART1_RX_0 [Place 30-374] IO placer failed to find a solution Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | IO Placement : Bank Stats | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | 0 | 0 | 0 | | | | | | | | 13 | 0 | 0 | | | | | | | | 34 | 50 | 33 | LVCMOS33(33) | | | +3.30 | YES | | | 35 | 50 | 41 | LVCMOS33(41) | | | +3.30 | YES | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | | 100 | 74 | | | | | | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ IO Placement: +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | BankId | Terminal | Standard | Site | Pin | Attributes | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 34 | Shield_I2C_scl_io | LVCMOS33 | IOB_X0Y1 | P16 | | | | Shield_I2C_sda_io | LVCMOS33 | IOB_X0Y2 | P15 | | | | Shield_SPI_io0_io | LVCMOS33 | IOB_X0Y29 | W15 | | | | Shield_SPI_io1_io | LVCMOS33 | IOB_X0Y46 | T12 | | | | d_dp0_dp13_tri_io[0] | LVCMOS33 | IOB_X0Y28 | U14 | | | | _dp0_dp13_tri_io[10] | LVCMOS33 | IOB_X0Y27 | U15 | | | | d_dp0_dp13_tri_io[1] | LVCMOS33 | IOB_X0Y43 | V13 | | | | d_dp0_dp13_tri_io[2] | LVCMOS33 | IOB_X0Y40 | T14 | | | | d_dp0_dp13_tri_io[3] | LVCMOS33 | IOB_X0Y39 | T15 | | | | d_dp0_dp13_tri_io[4] | LVCMOS33 | IOB_X0Y8 | V17 | | | | d_dp0_dp13_tri_io[5] | LVCMOS33 | IOB_X0Y7 | V18 | | | | d_dp0_dp13_tri_io[6] | LVCMOS33 | IOB_X0Y11 | R17 | * | | | d_dp0_dp13_tri_io[7] | LVCMOS33 | IOB_X0Y37 | R14 | * | | | d_dp0_dp13_tri_io[8] | LVCMOS33 | IOB_X0Y24 | N18 | | | | _dp26_dp41_tri_io[0] | LVCMOS33 | IOB_X0Y12 | R16 | | | | _dp26_dp41_tri_io[1] | LVCMOS33 | IOB_X0Y45 | U12 | | | | _dp26_dp41_tri_io[2] | LVCMOS33 | IOB_X0Y44 | U13 | | | | _dp26_dp41_tri_io[3] | LVCMOS33 | IOB_X0Y30 | V15 | | | | _dp26_dp41_tri_io[4] | LVCMOS33 | IOB_X0Y32 | T16 | | | | _dp26_dp41_tri_io[5] | LVCMOS33 | IOB_X0Y31 | U17 | | | | _dp26_dp41_tri_io[6] | LVCMOS33 | IOB_X0Y10 | T17 | | | | _dp26_dp41_tri_io[7] | LVCMOS33 | IOB_X0Y9 | R18 | | | | _dp26_dp41_tri_io[8] | LVCMOS33 | IOB_X0Y3 | P18 | | | | _dp26_dp41_tri_io[9] | LVCMOS33 | IOB_X0Y4 | N17 | | | | user_dio_tri_io[10] | LVCMOS33 | IOB_X0Y17 | W20 | | | | user_dio_tri_io[2] | LVCMOS33 | IOB_X0Y22 | N20 | | | | user_dio_tri_io[3] | LVCMOS33 | IOB_X0Y21 | P20 | | | | user_dio_tri_io[4] | LVCMOS33 | IOB_X0Y23 | P19 | | | | user_dio_tri_io[5] | LVCMOS33 | IOB_X0Y49 | R19 | | | | user_dio_tri_io[6] | LVCMOS33 | IOB_X0Y20 | T20 | | | | user_dio_tri_io[7] | LVCMOS33 | IOB_X0Y0 | T19 | | | | user_dio_tri_io[8] | LVCMOS33 | IOB_X0Y19 | U20 | | | | user_dio_tri_io[9] | LVCMOS33 | IOB_X0Y18 | V20 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 35 | Shield_SPI_sck_io | LVCMOS33 | IOB_X0Y62 | H15 | | | | Shield_SPI_ss_io | LVCMOS33 | IOB_X0Y88 | F16 | | | | btns_2bits_tri_i[0] | LVCMOS33 | IOB_X0Y91 | D20 | | | | btns_2bits_tri_i[1] | LVCMOS33 | IOB_X0Y92 | D19 | | | | rgb_led[0] | LVCMOS33 | IOB_X0Y55 | L15 | | | | rgb_led[1] | LVCMOS33 | IOB_X0Y68 | G17 | | | | rgb_led[2] | LVCMOS33 | IOB_X0Y58 | N15 | | | | rgb_led[3] | LVCMOS33 | IOB_X0Y99 | G14 | | | | rgb_led[4] | LVCMOS33 | IOB_X0Y56 | L14 | | | | rgb_led[5] | LVCMOS33 | IOB_X0Y53 | M15 | | | | _dp0_dp13_tri_io[11] | LVCMOS33 | IOB_X0Y75 | K18 | | | | _dp0_dp13_tri_io[12] | LVCMOS33 | IOB_X0Y72 | J18 | | | | _dp0_dp13_tri_io[13] | LVCMOS33 | IOB_X0Y61 | G15 | * | | | d_dp0_dp13_tri_io[9] | LVCMOS33 | IOB_X0Y83 | M18 | | | | dp26_dp41_tri_io[10] | LVCMOS33 | IOB_X0Y84 | M17 | | | | dp26_dp41_tri_io[11] | LVCMOS33 | IOB_X0Y77 | L17 | | | | dp26_dp41_tri_io[12] | LVCMOS33 | IOB_X0Y73 | H17 | | | | dp26_dp41_tri_io[13] | LVCMOS33 | IOB_X0Y71 | H18 | | | | dp26_dp41_tri_io[14] | LVCMOS33 | IOB_X0Y67 | G18 | | | | dp26_dp41_tri_io[15] | LVCMOS33 | IOB_X0Y81 | L20 | | | | user_dio_tri_io[0] | LVCMOS33 | IOB_X0Y82 | L19 | | | | user_dio_tri_io[11] | LVCMOS33 | IOB_X0Y80 | K19 | | | | user_dio_tri_io[1] | LVCMOS33 | IOB_X0Y86 | M19 | | | | vaux0_v_n | LVCMOS33 | IOB_X0Y97 | B20 | | | | vaux0_v_p | LVCMOS33 | IOB_X0Y98 | C20 | | | | vaux12_v_n | LVCMOS33 | IOB_X0Y69 | F20 | | | | vaux12_v_p | LVCMOS33 | IOB_X0Y70 | F19 | | | | vaux13_v_n | LVCMOS33 | IOB_X0Y63 | G20 | | | | vaux13_v_p | LVCMOS33 | IOB_X0Y64 | G19 | | | | vaux15_v_n | LVCMOS33 | IOB_X0Y51 | J16 | | | | vaux15_v_p | LVCMOS33 | IOB_X0Y52 | K16 | | | | vaux1_v_n | LVCMOS33 | IOB_X0Y93 | D18 | | | | vaux1_v_p | LVCMOS33 | IOB_X0Y94 | E17 | | | | vaux5_v_n | LVCMOS33 | IOB_X0Y65 | H20 | | | | vaux5_v_p | LVCMOS33 | IOB_X0Y66 | J20 | | | | vaux6_v_n | LVCMOS33 | IOB_X0Y59 | J14 | | | | vaux6_v_p | LVCMOS33 | IOB_X0Y60 | K14 | | | | vaux8_v_n | LVCMOS33 | IOB_X0Y95 | A20 | | | | vaux8_v_p | LVCMOS33 | IOB_X0Y96 | B19 | | | | vaux9_v_n | LVCMOS33 | IOB_X0Y89 | E19 | | | | vaux9_v_p | LVCMOS33 | IOB_X0Y90 | E18 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances It seems that I naively thought that those lines being commented out meant those signals weren't connected (shows how little I know!). Can anyone give me any pointers on how to overcome this, or how I should be doing this? Any help will be very gratefully appreciated. John