Arty XADC power supply monitor

[lvoudour]

Hello,

I got an Arty board about two months ago and I'd like to use the power supply monitor feature. My main question is:
"what's the appropriate sampling rate"

Never used a 7 series FPGA before so I started reading through the XADC user guide [UG480] and the Driving the Xilinx Analog-to-Digital Converter [XAPP795] note. From what I understand (correct me if I'm wrong):

• Both inputs must be set to unipolar
• The XADC should be operated in simultaneous sampling mode to sample both voltage and current at the same time
• No auto-calibration in this mode. Calibration is done once at power-on 
• The sampling rate should be low enough to cover the settling time of the analog input

Looking at the respective circuit

and assuming 12-bit accuracy, the settling time for the voltage sensing inputs [XAPP795,pp.2-8], [UG480,pp.79-80] is roughly

tset = 9.01 * (8.33K + 8.25K + 1K + 1K) * 10nF ~= 1.67ms

which implies sampling rates < 600 samples/sec if I don't want any gain errors. That's fine, but the problem is

1. the XADC cannot be used for other, faster inputs
2. we can't directly drive the XADC with the 100MHz board clock anymore, because the maximum ADCCLK divisor of 255 implies a minimum ~15Ksps/sec rate (not that big of an issue, plenty of PLLs in the chip - just worth mentioning)

The few options I see are:

• Forget about mixing monitoring and higher rate signals in the same design
• Lower the bit accuracy and use averaging
• Live with the error at higher rates and use averaging

Am I missing something here, do I have this whole thing completely wrong?
Has anyone successfully used the monitor inputs in the Arty? (couldn't find anything online)

Thanks,
Lymperis

[jpeyron]

Hi Lymperis,

Looking though the documentation you are correct in your evaluation of the situation. This explains some of behaviors we have been dealing with on our XADC projects we have been working on.

cheers,

Jon

[lvoudour]

Hi Jon, thanks for the reply.

Could you please elaborate on the problems you've faced with the XADC? Were there related to the power/voltage/current monitoring circuits on the Arty?

Since I can't find any projects online using those circuits I'll go ahead and try to test them myself. Unfortunately, I bought the Arty for personal use and I don't have the proper equipment at home to validate their accuracy/error. Anyway, I'll post here any findings for future reference in case someone else wants to use them

Regards,
Lymperis

[jpeyron]

Hi Lymperis,

Here is our IP core for the XADC on the Arty. I had recently talked to the person that made this demo and they had agreed with your evaluation of the XADC issue. Unfortunately they are not available to elaberate further on the behaviors that they saw. I reached out to our design engineer and they were able to get it sampling quicker than 600 samples/sec. during verification. I will research this and get back to you in the next few days. 

thank you,

Jon

[lvoudour]

Hi Jon,

You can definitely sample faster than 600 samples/sec, the problem is the faster you go the larger the accuracy error because of the big settling time. I'd be really interested on your engineer's input as I'm definitely not an expert in this area. By the way, another thing I noticed is that the INA199A1 datasheet lists the maximum output capacitive load as 1nF, but the Arty has a 10nF cap. I don't know what the effect is, but maybe it's worth mentioning it too to your engineer.

Thanks again,
Lymperis

[jpeyron]

Hi Lymperis,

Our design engineer and I looked further into this issue and found that you are correct about the 600 samples/sec with the settle time issue. When verifying the XADC we were sampling at 200 KSPS and did not see a difference compared to our ammeter, but we were averaging. So your evaluation of the situation is correct as well as your solutions. There is not an issue with the 10nF cap due to the 1K resister.

thank you,

Jon

[lvoudour]

All right, thank you Jon that's probably what I'm going to do (oversample and average)

Regards,
Lymperis

[rana_20]

Hi, 

I have a genesys2 board, I am trying to read power consumption of fpga using the embedded power monitor indicated in the reference manual. However, I do not know how to access the recorded values by the power monitor and log them into .csv file (what are the required tools, what should I be looking at). I also would like to sample power consumption values, along with temperature and other internal signal values. For temperature I use xadc, for internal signals monitoring I use ilacore and I read both using hardware manager, I was wondering how to sample power consumption simultaneously with the other measurements.

 

Thanks 

Rana

[jpeyron]

Hi @rana_20,

It looks like your question was answered here. If not please continue thread there.

cheers,

Jon