3 questions about the sampling rate, output, and state machine of the PmodMIC

[krb686]

I recently purchased the PmodMIC to use with my Nexys 3 board and Analog Discovery.  Finally after a bit of coding, I seem to have gotten it to run continuously, but I have just a few questions.


In the PmodMIC reference component PDF, it states:

 

The VHDL component is an entity named PmodMicRefComp which has five inputs and five outputs.The input ports are a 50MHz clock,....

 

(BTW, I think the 5 inputs, 5 outputs thing is a typo   ). 

But my first question is: 1)  Is it possible to lower the sampling rate? Apparently the 50 MHz input clock gets divided down to 12.5 MHz inside the PmodMICRefComp. I need to record some audio data, but certainly not at 12.5 MHz!  I am not sure why any audio source would ever need to be sampled that quickly, but in any case, I attempted to lower the input clock speed down a bit and my design seems to have failed.  I am looking to record signals comprised mainly of human speech, so 8KHz is actually about what I need.

The 2nd question is: 2)  I see no mention anywhere of the format of the data output by the PmodMIC.  It's 12 bits in parallel, but is that signed? unsigned? Couldn't seem to find this in the reference PDF anywhere.  If this is an SPI standard convention that I'm just not aware of, sorry for asking.

 

The 3nd question is: 3)  In the state machine diagram, is there no transition directly from the "SyncData" state to the "ShiftIn" state? My code currently initiates continuous sampling by checking if nCS is HIGH and DONE is low, as indicated in the SyncData state.  Then, it brings the START signal low again to return to the IDLE state, and increments a counter to keep track of the number of samples taken.  On the next clock cycle, it checks if START is low, and # of samples is > 1, then pull START highagain, repeating the process.



What I am wondering is: Instead of pulling START low to return to IDLE, would it not just be possible to keep START high and have nCS get pulled low again? I suppose this would need to be taken care of by the PmodMICRefComp VHDL code since that is the driver for the nCS signal after all.  It would be nice if that provided VHDL component had a single bit control signal that allowed for selecting ONE TIME conversion and CONTINUOUS conversion.


Thanks for taking the time to read this.
 

[Cristian.Fatu]

Before we answer the question, here is some more information that might be useful.

You may understand this device as being similar to an AD converter. It provides a digital output, on a number of bits. You should consider this value as an unsigned value (between -0 and 2**12 - 1), but you can as well have other approach in considering the value of these bits.

I am directing you to an application that does some data acquisition https://www.dropbox.com/s/pd83chcqczeimph/Data%20Acquisition%20System%20-%20Demo%20Project.zip?dl=0. As an alternative, the AD converter can be replaced with a PmodMIC (read "Optional: Audio Recorder" on page 11 of the documentation).

1) Yes, you can lower the sample rate. The way it works now is that the clk_counter (the counter used in order to divide the 50 MHz clock) is implemented on 2 bits and divides 50 by 4. You can extend its representation on more bits and thus you can implement higher division rate (and lower sample rate).

2) Please read the explanation I gave at the beginning of this message as well as the previous post in this topic.

3) Yes, the current implementation uses no transition directly from the "SyncData" state to the "ShiftIn" state (as you saw in NEXT_STATE_DECODE). You can always modify and implement your approach.

We admire (and encourage) your approach of understanding and customization of this component. 

[JColvin]

Hi krb686,

 

I am personally not familiar with VHDL, so I'll have to ask some other people here at Digilent, but I can answer your second question.

 

The PmodMIC with its 12-bit ADC will send out its the 12 bits of data in Serial over SPI with the MSB first. This data will be unsigned (because of the nature of the ADC), and be sent out as the last 12 bits of the two bytes that the PmodMIC sends out.  You can find out more from the PmodMIC reference manual from our wiki page.

 

Thanks,

JColvin