Difficulty implementing Nexys 4 DDR OOB project (synthesis runs okay !).

[Nevermnd]

Hi,

So I was able to create the requisite project file from the zip listed here: https://digilent.com/reference/learn/programmable-logic/tutorials/nexys-4-user-demo/start?_ga=2.32623421.226966298.1711761135-1072968436.1711761135

via source ./create_project.tcl (Note: I also tried downloading the most recent release via the Git repo, but unfortunately that release does not include the required .tcl file).

I can run synthesis ok, but when I try to implement I am getting the following errors:

I am not sure what I am missing.

Edited April 1 by Nevermnd

[Nevermnd]

Okay...

So after a great deal of 'mucking about' I finally got this resolved using Vivado 2020.1 (unfortunately trying to install 2016.4 which the project was originally written for does not immediately remedy the situation either).

So beyond running the create_proj.tcl file via source ./creat_proj.tcl as described in the docs (and which, notably though this distro has a more recent release than the original, the github repo for that version has no such .tcl file-- So I had to make do with the 2016 Zip file not on Git), while synthesis works, implementation will fail.

Reason being because the IP, though now attached to the project is 'black boxed' or 'locked'-- So you have to go to the IP Sources panel first and 'Upgrade IP' for each of the modules as well as generating the associated code.

With that done, even if you have the board properly specified, if you try to make use of the Nexys-4-DDR-Master.xdc constraints file via the board constraints master on Github, your generation of the Bitstream will also fail. You *must* use the constraints file provided with the project 'Nexys4DDR_C.xdc' and then *finally* it will compile load and run/let you program.

I also noticed I happened to ask basically the same question a couple of years ago and I either forgot, or perhaps more likely at that time just gave up.

Honestly, it is a bit unfortunate, as I feel Digilent makes good quality products-- Yet needless to say the documentation leaves quite a bit to be desired. Or, at the least, if proj files were included, or after running associated TCL scripts the thing would just work-- For example projects, honestly I think that would mean a great deal.

Granted, I realize probably 90-95% of people playing with these devices are probably doing so as part of a formal college class, where a more knowledgeable instructor is ready at hand-- Rather than like myself, who is trying to teach themselves how to work with FPGAs all on their own.

Thus, I must admit this process has been rather quite frustrating, but at least for anyone that experiences something similar: That's how you do it/fix it.

[JColvin]

Hi @Nevermnd,

I apologize for the delay. I don't know if it was a typo on your part, but I think the main problem you ran into is that you have the Nexys 4 DDR (now known as the Nexys A7), but, at least based on the link you provided, you were working with the "Nexys 4" which does not have the on-board DDR memory.

The correct link for the Nexys 4 DDR / Nexys A7 OOB demo (also accessible from it's Resource Center) is here: https://digilent.com/reference/programmable-logic/nexys-a7/demos/oob. The more recent releases, including 2023.1, give you a completed project that will already have the correct .xdc included, and only need you to click "Generate Bitstream", rather than making you go through the whole create_proj.tcl process.
On my machine at least, I was able to generate the bitstream without errors.

Feel free to let me know if you have any additional questions or feedback about the process at large.

Thanks,
JColvin

[Nevermnd]

@JColvin

Okay, well the board I have is strictly branded Nexys 4 DDR.

I know that the DDR4 uses the same Artix class processor as the A7, but since the DDR4 is listed as 'discontinued/replaced by' the A7, obviously I did not presume the HDL, or particularly constraints file, would be somehow compatible. 

I mean I also have a Basys 3 and an Analog Discovery 2 from you guys, thus my comment... But I am not an EE student. I've been in Data Science, so this has been my 'weekend, let's try to have some fun & learn something new !' kind of thing.

Edited April 12 by Nevermnd

[JColvin]

Hi @Nevermnd,

The Nexys 4 DDR and the Nexys A7 are identical products for all intensive purposes (there might be transparent changes that I am unaware of that aren't branding related). There are a couple of threads on this topic here and here, though clearly this never actually made it into the Resource Center(s), or as a comment into the board files, .xdc, or other HDL materials. I will see about getting that clarified.

For what it's worth, my FPGA also has the Nexys 4 DDR silkscreen label and have never encountered an issue using materials labeled for Nexys A7 instead.

As for why the product branding changed at all for Digilent (or any other company; see Xilinx AMD or National Instruments NI / Emerson), that's because stakeholders with the power said to make the change and the rest of us said 'yes boss'.

Regardless, I'm glad to see you are willing to try out the board while being in Data Science. It's probably an easier climb than coming from Chemical Engineering like I did.

Thanks,
JColvin