Nevermnd

@JColvin Okay, well the board I have is strictly branded Nexys 4 DDR. I know that the DDR4 uses the same Artix class processor as the A7, but since the DDR4 is listed as 'discontinued/replaced by' the A7, obviously I did not presume the HDL, or particularly constraints file, would be somehow compatible. I mean I also have a Basys 3 and an Analog Discovery 2 from you guys, thus my comment... But I am not an EE student. I've been in Data Science, so this has been my 'weekend, let's try to have some fun & learn something new !' kind of thing.

Okay... So after a great deal of 'mucking about' I finally got this resolved using Vivado 2020.1 (unfortunately trying to install 2016.4 which the project was originally written for does not immediately remedy the situation either). So beyond running the create_proj.tcl file via source ./creat_proj.tcl as described in the docs (and which, notably though this distro has a more recent release than the original, the github repo for that version has no such .tcl file-- So I had to make do with the 2016 Zip file not on Git), while synthesis works, implementation will fail. Reason being because the IP, though now attached to the project is 'black boxed' or 'locked'-- So you have to go to the IP Sources panel first and 'Upgrade IP' for each of the modules as well as generating the associated code. With that done, even if you have the board properly specified, if you try to make use of the Nexys-4-DDR-Master.xdc constraints file via the board constraints master on Github, your generation of the Bitstream will also fail. You *must* use the constraints file provided with the project 'Nexys4DDR_C.xdc' and then *finally* it will compile load and run/let you program. I also noticed I happened to ask basically the same question a couple of years ago and I either forgot, or perhaps more likely at that time just gave up. Honestly, it is a bit unfortunate, as I feel Digilent makes good quality products-- Yet needless to say the documentation leaves quite a bit to be desired. Or, at the least, if proj files were included, or after running associated TCL scripts the thing would just work-- For example projects, honestly I think that would mean a great deal. Granted, I realize probably 90-95% of people playing with these devices are probably doing so as part of a formal college class, where a more knowledgeable instructor is ready at hand-- Rather than like myself, who is trying to teach themselves how to work with FPGAs all on their own. Thus, I must admit this process has been rather quite frustrating, but at least for anyone that experiences something similar: That's how you do it/fix it.

Hi, So I was able to create the requisite project file from the zip listed here: https://digilent.com/reference/learn/programmable-logic/tutorials/nexys-4-user-demo/start?_ga=2.32623421.226966298.1711761135-1072968436.1711761135 via source ./create_project.tcl (Note: I also tried downloading the most recent release via the Git repo, but unfortunately that release does not include the required .tcl file). I can run synthesis ok, but when I try to implement I am getting the following errors: I am not sure what I am missing.

Hey all, So I wasn't quite sure if I should ask this on the Vivado forum, or here... However, I do have two Digilent Boards, the Basys 3 and Nexus 4 DDR. I've basically been trying to 'self teach' myself FPGA via a textbook: Digital System Design with FPGA Implementation But I've been struggling a bit with the 'compiling/implementation' step. Grant I am using Vivado 2018.2 (I know there are obviously much more recent versions, but the install is *huge*-- I mean 225-250 GB?!? You *must be kidding me*), And this should be just enough for my simple purposes. In any case, #1 I realized I had to manually install the board packages, which I think I have done successfully. #2 Even though the related IP is explicitly stated in the code, I realized I have to manually add the IP to the project-- Having done so now it will run simulation, even synthesis: But when I get to the last step, implementation, it is 'bugging out' and I'm really not sure what is wrong. The code itself is two files, so a bit long to directly include here, but as stated, does come from a textbook, so I hope that's 'not wrong'. It is a simple VGA display 'test application' I think I may have just not configured the IP right when I added it, but I didn't think that should be 'something you have to think about', if you already 'call it up in the code'. In any case, any help would be appreciated, as like I said I am 'learning this on my own', so I have no 'professor' to ask about it. And, even, the response it provides about the VCC clock not being connected is fairly clear... But I am still like 'what?' Best, -A