Switch from Nexys 4 DDR to Nexys A7

[Axolotl]

 

I have a question regarding the Nexys 4 DDR and his successor the Nexys A7:

Will a working VHDL-Program, written for the Nexys 4 DDR XC7A100T-1CSG324C, work on an Nexys A7 XC7A100T-1CSG324C?

(written in VHDL constructed in Vivado, using the constraint-file „Nexys-4-DDR-Master“ from your resource center [https://github.com/Digilent/digilent-xdc/] )

Is it possible to simply generate the Bitstream of this Program (made for the Nexys 4 DDR XC7A100T-1CSG324C) and download it onto the Nexys A7 XC7A100T-1CSG324C without making any changes to the code?
Even if the Constraint-File for the Nexys-4-DDR-Master is used?

The only difference in the Constraint-Files of the boards is the IOStandard for the Pmod Header JXADC, changed from LVDS to LVCMOS33.
There shouldn‘t be any Problems since the voltage range of the previously used LVDS is within the range of the voltage for the LVCMOS33, right?
 

Will a VHDL-Program that doesn‘t even use the Pmod Header JXADC work without problems?
Or do I still have to alter something in my existing programm to make it work on a Nexys A7 XC7A100T-1CSG324C?

Thanks in advance!

 

[JColvin]

Hi @Axolotl,

One bitstream generated for the Nexys 4 DDR will be able to work as is with no changes to the code or .xdc file on the Nexys A7. This will include the JXADC which (for some reason unknown to me) is listed as LVDS despite the associated bank being powered at 3.3V. If a design does not use a particular part of the board, be it the JXADC or something else, as long as the pins that are being used match, then it will be good to go.

Thanks,
JColvin