Genesys ZU-5EV Setting VADJ to 1.8V

[RyanW]

Hello, I am a little confused on how to set the VADJ on the Genesys XU-5EV. According to the reference manual external VADJ_LEVEL1 and VADJ_LEVEL0 signals control the state of VADJ. How can I ensure that these two signals both are signaled to 1 and 1 upon boot. I suppose I will need to ensure these signals reach their levels before the platform management starts its booting process. What are the tips on this as I really need the capability of easily getting 1.8V on the LPC FMC and the usage of the video codec unit; otherwise I would consider the ZedBoard option with jumper headers for VADJ. I do not yet have the board to play around with, so some of this is still just conceptually abstract to me.

[JColvin]

Hi @RyanW,

My understanding is that the firmware on the Platform MCU which controls the state of VADJ will by default/on power up will have the VADJ rail disabled until it parses the EEPROM memories of the attached device to determine the correct VADJ to use. An LED fault indicator will be shown and the VADJ rails will remain disabled if no compatible VADJ voltage is found (such as if an FMC mezzanine module and SYZYGY pod have mismatched values, or request a VADJ that the Genesys ZU is not able to supply).

I have asked another engineer more familiar with the Genesys ZU what additional actions you can take to help ensure the correct voltage upon power up.

Thanks,
JColvin

[thinkthinkthink]

You can force a certain VADJ level with xlconstant or gpio IPs in your block design. Check out the 5ev/oob/master branch of our Genesys ZU repo that contains the board's out-of-the-box demo.

Also,  take a look at the XDC file of that OOB project, more specifically lines 227 through 237.

Edited November 17, 2023 by thinkthinkthink

[zygot]

The Genesys XU-5EV has one Vadj rail out of its power supply design. It has two interfaces requiring Vadj; 1 FMC and 1 SYZYGY.

The concept of SYZYGY is that the carrier board is supposed to supply independent logic supplies for each SYZYGY port that it has. SYZYGY has a negotiation protocol between the carrier board and each SYZYGY pod that allows the carrier board to set each Vadj in a way that is within the limits of each pod and the capabilities of the carrier board power supply. This implies that with a number of different SYZYGY pods you aren't guaranteed a specific Vadj for all of them, just that itmight be possible for some combination of Vadj voltages to accommodate different pods at the same time,

FMC mezzanine cards might have an EEPROM or not. There is no DNA protocol for negotiation of Vadj rail voltages. Not all FMC mezzanine cards for FPGA boards closely conform to Vita standards.

The fact that Digilent conflated the SYZYGY and FMC interfaces with into one Vadj may well be problematic if you need to use both an FMC carrier card and a SYZYGY pod requiring different Vadj voltages. This is something to consider before making a purchase.

Another thing to consider is that IO on UltraScale devices is not the same as on Series 7 devices. Even DDR is more complicated and is dependent on vendor IP and behind the curtains vendor tool software. Before considering UltraScale for a project I highly advise reading though the UltraScale IO documentation. Edited November 17, 2023 by zygot

[zygot]

RyanW: "The goal is eventually to develop a daughter board for the Kria"

Take the complexity of the UltraScale family and add custom device variants with no detailed documentation ( Aka Kria ) and you are asking for problems, in my humble opinion.

As I mentioned do take the time to do a careful read of UltraScale documentation, particularly IO. Unless you have an NDA with AMD providing information about their Kria devices that isn't public knowledge, barging ahead with a custom design for those SOMs seems rather risky to me. Near as I can tell the Kria concept is to provide cheap application specific hardware that isn't open source friendly.

[edit] Before pinning your hopes on the video codec found on certain UltraScale ZYNQ devices, I'd advise researching actual support and use cases for this capability. In general there are a lot of not well advertised restrictions on such functionality in my experience. Edited November 17, 2023 by zygot

[RyanW]

28 minutes ago, thinkthinkthink said:

You can force a certain VADJ level with xlconstant or gpio IPs in your block design. Check out the 5ev/oob/master branch of our Genesys ZU repo that contains the board's out-of-the-box demo.

Also,  take a look at the XDC file of that OOB project, more specifically lines 227 through 237.

So is this to say that the Platform MCU can re-assign bank voltages after the FPGA has been programmed? I thought that the bank voltages would need to be powered during the bitstream process. So if I can force the Platform MCU to reassign the bank voltages, does that mean I should be setting that in the PL and that the bank voltages on Zynq can be swapped after programmed?

[RyanW]

8 minutes ago, zygot said:

FMC mezzanine cards might have an EEPROM or not. There is no DNA protocol for negotiation of Vadj rail voltages. Not all FMC mezzanine cards for FPGA boards closely conform to Vita standards.

This complexity may be problematic for me. I need to create my own simple FMC card to connect to some custom 16 channel LVDS interface. I really need something that can get to this without extra steps on a devboard. The ZedBoard could do this for me and I have experience using basic Zynq devices, but I really need the Video Codec Unit eventually. The Ultrascale+ MPSoC devices do scare me a bit, because it seems its always different and more complicated whenever I look at boards for it and I am worried I will run into roadblocks that take too much time to solve. The goal is eventually to develop a daughter board for the Kria, whether by contracting it out, or by me taking a stab at it. It seems that the XCZU5EV-SFVC784-1-E chip on the Gensys is very close to the Kria chip, so I am hoping to use this board to get developing things without daughter board roadblocks on the Kria devkits (can't get the right voltages/IO on the AI or Robot starter kit). I'm trying not to run into that problem again. a 1.8V HP bank (or even a 2.5V HR) would be perfect for my use cases.