Done pin is not high..

[Niranjana]

I am trying to launch a program in Xilinx vitis..But the following error is popping up. 

I am using Zybo Z7020, and my program is based on connecting PS and PL through UART protocol.

[JColvin]

Hi @Niranjana,

This message appears when the FPGA / SoC has not been configured with a bitstream. More recent versions of the Xilinx software have made it so that when you choose to launch an application it will automatically load the bitstream for you prior to launching (used to be that you had to manually configure the device with the bitstream).

I don't know which version of the Xilinx / AMD toolchain you are using, but you can still manually configure the device with a bitstream by clicking Xilinx / Vitis dropdown at the top (next to File, Edit, etc) and choose the Program Device option.

Presuming you first created a hardware specification (block design) in Vivado and imported it into Vitis, my guess as to why Vitis is not automatically finding the bitstream is because after exporting the hardware platform, the include bitstream option was not checked.

Let me know what you learn.

Thanks,
JColvin