Genesys-2 board: how to force longer CAS latency for DDR3?

[dyne21]

Hello,

 

Board: Genesys-2, Vivado 2019.1

I found the default DDR3 CL was set to 13 at 900MHz from MIG. If I want to increase it to 14, what is the correct way?

Is it achievable with modifying .prj file? I found many .prj files in my project folder as below. Please advise the correct way.

ubuntu@ubuntu:~/Xilinx/Vivado/2019.1/Genesys_2_QSPI_backup$ find . -type f -name "mig*.prj"
./Genesys_2_QSPI.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/mig.prj
./Genesys_2_QSPI.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_b.prj
./Genesys_2_QSPI.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/mig_a.prj
./Genesys_2_QSPI.ip_user_files/mem_init_files/mig_b.prj
./Genesys_2_QSPI.ip_user_files/sim_scripts/design_1/ies/mig_b.prj
./Genesys_2_QSPI.ip_user_files/sim_scripts/design_1/xsim/mig_b.prj
./Genesys_2_QSPI.ip_user_files/sim_scripts/design_1/questa/mig_b.prj
./Genesys_2_QSPI.ip_user_files/sim_scripts/design_1/activehdl/mig_b.prj
./Genesys_2_QSPI.ip_user_files/sim_scripts/design_1/modelsim/mig_b.prj
./Genesys_2_QSPI.ip_user_files/sim_scripts/design_1/xcelium/mig_b.prj
./Genesys_2_QSPI.ip_user_files/sim_scripts/design_1/riviera/mig_b.prj
./Genesys_2_QSPI.ip_user_files/sim_scripts/design_1/vcs/mig_b.prj

Thanks.

Edited August 10, 2023 by dyne21
information missed.

[zygot]

You can create your own custom target memory device in the MIG tool and specify any parameter setting that you want to experiment with.

Edited August 11, 2023 by zygot

[asmi]

On 8/9/2023 at 9:55 PM, dyne21 said:

I found the default DDR3 CL was set to 13 at 900MHz from MIG. If I want to increase it to 14, what is the correct way?

Can you please let us know why would you want to do that? Just curious.

[JColvin]

Hi @dyne21,

Zygot is correct that you would need to create your own custom part within the MIG tool to specify these custom parameters, to which you would then hopefully be able to generate a bitstream.

Though I too am curious why are wanting to change the DDR3 manufacturer recommended CL to a different value. I can guess at reasons of course, but they will still only be guesses on my end.

Thanks,
JColvin