Should "Max. clock period" be "Min. clock period"?

[zzzhhh]

In section 5.1 DDR3L of Arty A7 Reference Manual (link), Table 2 says the "Max. clock period" is 3000 ps. But I think 3000 ps should be the "Min. clock period" because we can further increase the clock period (= reduce clock frequency) to like 6000 ps shown below by Recommended Input Clock Period in the same table. If you are an employee of Digilent, can you please double check it? Thanks.

[asmi]

"Recommended Input Clock Period" refers to the frequency of the clock which is going into the MIG block, while "Max. clock period" refers to actual DDR3 bus frequency. A per Micron's datasheet, DDR3 has a minimum period of 3.3 ns, so the lowest possible DDR3 frequency is 300 MHz. You can theoretically run it slower, but that will be outside guaranteed regime and so it may or may not work. The reason why there is a minimum frequency is because DDR3 memory devices contain DLL (which is used internally to adjust signal timings), and all PLLs and DLLs have finite working envelope.

From the practical standpoint, I don't really see an upside in running DDR3 at slower frequency than the maximum, as you simply leave a potentian bandwidth on a table.

[zygot]

On 5/20/2023 at 12:23 AM, zzzhhh said:

In section 5.1 DDR3L of Arty A7 Reference Manual

This refers to the Artix 35T version which has been discontinued. The DDR clocking capabilities of the L part are slower than for the regular speed and power grades. Asmi is correct that there are lower limits to how fast you want to run your DDR3 memory CLK. It's how DDR3 works. It wouldn't be a bad idea for anyone wanting to use DDR in a design to educate themselves about such things. For some Artix devices you are limited to a 2:1 MIG controller design, which is what the reference provides for.

For the reference that you are using the 6000ps input clock is the source clock for the MIG controller clocking. So, if you provide a 166.7 MHz input clock and have a 2:1 memory controller design your DDR CLK will be 333 MHz and you will have a 667 Mbps DQ data rate. That's as good as it gets for the XC7A35TICSG324-1L part.

If you've purchased you board recently check the part number on the FPGA device as it's likely a larger part that isn't low power.

I'm fairly certain that the "Max. clock period" in the reference manual is a poor choice of words because not many customers want to know how slow they can run the DDR PHY clock. For the XC7A35TICSG324-1L I suppose that max clock period and min clock period are pretty much the same as this is the lower end for the DDR3 chip and the upper end for the FPGA device.

Feel free to ignore all of the posts to your question so far and wait for someone from Digilent to tell you the same things.

Edited May 22, 2023 by zygot

[artvvb]

There's a lot more detail on what the different clocks involved are that can be found in UG586, "Clocking Architecture" starts on page 120: https://docs.xilinx.com/v/u/en-US/ug586_7Series_MIS. As asmi and zygot mentioned, the distinction between the interface data rate (the first clock period spec) and system clock input (second period spec) is critical.

That said, I think this is still a mistake in the manual - it should be maximum transfer rate or similar - but am happy to be corrected. You can see the same spec for other boards (Nexys A7 for example) listed with a maximum clock period less than a recommended clock period.

The limit is mainly relevant because the allowed selection in the MIG is 3000 ps to 3300 ps instead of 2500 to 3000 ps. There's a warning that pops up for values below the range. See blue text, below.

I found the DDR3L Micron datasheet here, for reference: https://www.micron.com/products/dram/ddr3-sdram/part-catalog/mt41k128m16jt-125. Of particular interest are the speed bins tables, table 72 and table 73, CL=5, CWL=5.

Thanks,

Arthur

[zzzhhh]

On 5/22/2023 at 2:51 PM, zygot said:

This refers to the Artix 35T version which has been discontinued. The DDR clocking capabilities of the L part are slower than for the regular speed and power grades. Asmi is correct that there are lower limits to how fast you want to run your DDR3 memory CLK. It's how DDR3 works. It wouldn't be a bad idea for anyone wanting to use DDR in a design to educate themselves about such things. For some Artix devices you are limited to a 2:1 MIG controller design, which is what the reference provides for.

For the reference that you are using the 6000ps input clock is the source clock for the MIG controller clocking. So, if you provide a 166.7 MHz input clock and have a 2:1 memory controller design your DDR CLK will be 333 MHz and you will have a 667 Mbps DQ data rate. That's as good as it gets for the XC7A35TICSG324-1L part.

If you've purchased you board recently check the part number on the FPGA device as it's likely a larger part that isn't low power.

I'm fairly certain that the "Max. clock period" in the reference manual is a poor choice of words because not many customers want to know how slow they can run the DDR PHY clock. For the XC7A35TICSG324-1L I suppose that max clock period and min clock period are pretty much the same as this is the lower end for the DDR3 chip and the upper end for the FPGA device.

Feel free to ignore all of the posts to your question so far and wait for someone from Digilent to tell you the same things.

Of course I will ignore your garbage. Also, since you know I will ignore it, don't put your ignorant garbage in my question in the future.

[zygot]

5 hours ago, zzzhhh said:

Of course I will ignore your garbage. Also, since you know I will ignore it, don't put your ignorant garbage in my question in the future.

I don't think that you quite grasp the meaning of "ignore".

Instead of posting nonsensical vitriol I'd be impressed if you could put forth a cogent argument as to what, specifically, about anything that I've posted in response to your question here that you find to be "ignorant garbage". Please do take the opportunity to correct any misinformation that's been posted to this thread. This is your chance to make yourself a useful member of the Forum community. No one cares about how you feel. Readers might care about what you know, if it's technically supportable with facts. If all you want to do is vent shear nonsense I think that there's a place for that... perhaps Twitter? The Digilent Forums are not the plce to embarrass yourself with such outbursts.

Again, anyone can post reasonable answer to questions, regardless of how vague, to public posts.

Edited June 13, 2023 by zygot