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Of course I will ignore your garbage. Also, since you know I will ignore it, don't put your ignorant garbage in my question in the future.

In section 5.1 DDR3L of Arty A7 Reference Manual (link), Table 2 says the "Max. clock period" is 3000 ps. But I think 3000 ps should be the "Min. clock period" because we can further increase the clock period (= reduce clock frequency) to like 6000 ps shown below by Recommended Input Clock Period in the same table. If you are an employee of Digilent, can you please double check it? Thanks.

Thank you and other guys discussing interrupt on MicroBlaze. I was also stuck at first with my own AXI4 peripheral IP which outputs interrupt signal. Your SDK code helped me find out what I was missing. PS, in my Vivado/Vitis 2022.2.2 project, calls to XIntc_MasterEnable and microblaze_enable_interrupts are not needed. And I call XIntc_LookupConfig before XIntc_Initialize. Finally, the second argument of Xil_ExceptionRegisterHandler should be the ISR function because INTC_HANDLER is undefined in current version of Vitis. I'm pretty surprised that we still need to call exception related APIs since I think I have done all the initialization and configuration work for interrupt, so why bother setting up exception? This is what I was missing. It's so sad to see you go, Jon. I can't imagine a current Digilent staff could carefully read a customer's question, not to mention creating a working project to answer the question.

I embedded a MicroBlaze core in the FPGA of Arty A7-100T board. To measure time spent by a piece of code run by MicroBlaze core in Vitis, I tried #include <time.h> clock_t start, end; start=clock(); // code to be measured end=clock(); But I received error So, is there any API from Vitis SDK I can use to measure time using MicroBlaze core in Vitis for Arty A7-100T? If answer is no, is that because of the limitation of MicroBlaze? If so, if I replace MicroBlaze with some other processor core, say RISC-V, can I measure time in Vitis? Or, is there no hope at all to do time measurement using C code in Vitis on top of Artix-7 FPGA?

I was not asking you.

Thank you all guys for replies. @artvvb: May I follow up with a few more questions based on your reply? First, from your surprise, both UARTLite IP and the USB to UART bridge (a Cypress chip I don't remember) are supposed to be able to transfer large file from host PC to the Arty A7-100T board, right? If so, I'll double check my code; maybe there is some bug in my code which uses low-level driver APIs. Second, I am using the default polling mode for quick start of the development. Do you mean interrupt mode can avoid possible data loss? Third, for UART data transfer from host PC to the board using Tera Term, do you happen to know whether Tera Term will pause and hold the data in the file being sent when it detects that the UART FIFO is full? On the other hand, for data transfer from the board to host PC, does MicroBlaze or UARTLite IP or the USB to UART bridge will pause and hold the data or just discard the data when it detects that the UART FIFO is full? I have no control over Tera Term, but I can control the program transferring data from board to host. If MicroBlaze doesn't hold when sending data, I can add some sleep in the code to make sure there are always space in the FIFO. Do you have some suggestion of how long I should sleep after sending each byte? Finally, kind of off-topic, I hope Digilent can release some (working and correct) tutorials like UART transmission which is more easy to follow and to learn than documents. Users have their own work to do, and do not have time and necessity to learn technicality and specificity of UART or Ethernet port or DDR3 memory controller. Just tell us (working and correct) steps; no tons of theories and explanations. For now the only working and correct tutorial is the baremetal one I referred to in my question. All others like Ethernet echo server are either simply not working or unavailable. Can you guys in Digilent please update and add these tutorials so that we can focus on our own work after paying so much dollars? I don't think that's extremely hard. Thanks a lot.

I am using Digilent Arty A7-100T board and Vivado/Vitis 2022.2.2 on Windows. First I followed this tutorial to build a baremetal system having a MicroBlaze processor and external DDR support. Then I drag and drop a USB UART from the Board tab into the block design diagram and apply the auto connect wizard to complete the hw design. After successfully passing the compiling and bitstream generation, I exported the hardware and created an application in Vitis in order to transmit a large file between host PC and the board through USB UART. The program on Vitis is as follows: #include <stdio.h> #include "xaxidma.h" #include "xuartlite.h" #include "xparameters.h" #include "xil_printf.h" #define fileSize 3220 int main(){ print("Hello World\n\r"); u8 * imageData; imageData = malloc(fileSize); for (int i=0;i<fileSize;i++) { scanf("%c", imageData+i); xil_printf("%c", imageData[i]); } free(imageData); return 0; } To test, I use Tera Term as serial terminal because it supports sending file. I created a large text file and run the program. But there are data loss based on the output. I also tried low-level UARTLite code for the same purpose: u8 * imageData; u32 receivedBytes, totalReceivedBytes=0, sentBytes, totalSentBytes=0; XUartLite_Config *myUartConfig; XUartLite myUart; u32 status; myUartConfig = XUartLite_LookupConfig(XPAR_AXI_UARTLITE_0_DEVICE_ID); status = XUartLite_CfgInitialize(&myUart, myUartConfig, myUartConfig->RegBaseAddr); if (status == XST_SUCCESS) print("UART initialization succeeds\n\r"); while (totalReceivedBytes<imageSize) { receivedBytes = XUartLite_Recv(&myUart, imageData+totalReceivedBytes, 1); totalReceivedBytes += receivedBytes; } But I encountered the same data loss. I set the baud rate to 9600 and I cannot see anything wrong in other parts of the hw/sw design. So, if you did the same thing correctly on Arty A7-100T board using Vivado/Vitis 2022.2.2 on Windows, how did you transmit large file between host PC and the board through USB UART? Is this because the limitation or bug of UARTLite IP in Vivado? Or, is the USA UART interface of this board designed to be unable to transmit large file?

Except Digilent staffs, some people do not reply in order to answer a question. They only come here to show off. Even after finishing the reply, they still do not know what the question is. Their reply can do nothing but confuse the asker by complicating simple things, with a mild threat. I hope the asker can be smart enough to identify such a people.

Seems that this topic was discussed in length long long ago and MicroBlaze + FreeRTOS + lwIP Echo Server on Arty-7 board once worked: But unfortunately it is not working now. So I continue to ask whether someone, anyone, ever make it under most up-to-date 2022.2.2 version of Vivado/Vitis on Windows 10? Thanks a lot.

I think a low-end Arty A7-100T is more than enough. A book "Architecting High-Performance Embedded Systems: Design and build high-performance real-time digital systems based on FPGAs and custom circuits" written by Jim Ledin uses this board to implement a digital oscilloscope sampled at 100 MHz with 14 bits of resolution. Digilent is offering 15% discount right now. Note however that the step-by-step tutorial of baseline Vivado project (the same as this Digilent tutorial) in this book does not work under current version of Xilinx Vivado/Vitis software (2022.2.2). I still don't know how to use the Ethernet of this board, and you can get no technical support in this regard from Digilent or Xilinx. If you somehow get through this tutorial, I would greatly appreciate it if you can share with us how you make it.

Thanks for being on it. I can get through the Vivado part. But just can't get through the Vitis part even if I exactly followed the steps. The errors I encountered is 1) DHCP does not work, 2) telnet cannot connect to the server. The error messages I obtained in Vitis Serial Terminal are: Do you have some quick suggestions? I'm using Vivado/Vitis 2022.2.2 on Widows 10.

The tutorial is https://digilent.com/reference/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze-servers/start. If you follow it, you'll see this tutorial is erroneous under current version of Vivado and Vitis 2022.2.2. So, is there any chance for Digilent to update it so that your customers can follow it without errors? Thanks. Meanwhile, can you please add a note in red at the beginning of the webpage "This tutorial is erroneous. Please don't follow it in Vivado and Vitis 2022.2.2"? That can at least avoid wasting plenty of time of your customers. Thanks.

Thank you for the reply and recommendations therein. I have an additional question about the function of "Olimex ARM-USB-TINY-H USB Programmer". If we can use a micro-B USB cable to program FPGA and Flash on the development board through USB JTAG interface, why can't we use the same cable and interface for RISC-V programming? What is absolutely necessary to use Olimex ARM-USB-TINY-H USB Programmer instead of a USB JTAG for RISC-V programming on FPGA? Thank you.

artvvb's reply reveals the root cause. The original design in which I got the same BACKBONE error sends clock signal from a clock wizard to MIG, not from MIG to clock wizard required by the recent Vivado (like Vivado 2022.2.2 I am using). After I reverse the clock path, the BACKBONE error disappears. artvvb, can you please, however, explain to us why we should send clock signal from MIG to other downstreaming components if we don't wanna see the BACKBONE error? Also, I have another question about picking clock connection here: Why "Do not select the system clock input to the MIG"? Can you please answer? I'm a verified buyer of Digilent product. Thanks a lot.

In "Getting Started with Vivado and Vitis for Baremetal Software Projects" tutorial, we are warned "Do not select the system clock input to the MIG." if MicroBlaze and DDR are used. What's wrong with the system clock?