CMOD-A7 -- accessing the on-board SPI flash directly

[biosbob]

once i indirectly program the SPI flash with my FPGA configuration via JTAG, is there a way to access the SPI flash directly????

i have some extra data i'd like to store in the flash (above the configuration), and want to erase/program unused sectors *without* have some logic on the FPGA do it for me....

[asmi]

Yes you can - take a look at Xilinx's Quad SPI IP.

[artvvb]

Hi @biosbob

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and want to erase/program unused sectors *without* have some logic on the FPGA do it for me....

FPGA logic, such as the mentioned Quad SPI IP, is required to access the flash. As I understand it, the way that Vivado writes to flash via JTAG is actually by putting a pregenerated bitstream into the FPGA that creates a bridge between the JTAG circuitry and the flash's SPI interface.

Thanks,

Arthur

[biosbob]

 

is there any way to (easily!!!) get to pins K19, D18, etc on my dev-board????  if so, then i can access the SPI FLASH directly (without intervention from the FPGA)....  i can see this being complicated, however; but i thought i'd at least ask the questions....

somewhat related, is there external access to UART_TXD_IN and UART_RXD_OUT (pins J17 and J18)????

[asmi]

All QSPI lines except for clock are always user I/O pins, so your design can always use them, as for the clock, Xilinx provides a special primitive STARTUPE2 which allows user designs to output the clock for the QSPI flash, however specifically in the case of CMOD, they've connected another user I/O pin to the clock line such that your design can output clock through that pin directly (vs via STARTUPE2 primitive). All dual-purpose pins are completely in the user design's hands once configuration is over, FPGA itself will never interfere in any way.

[asmi]

2 hours ago, artvvb said:

As I understand it, the way that Vivado writes to flash via JTAG is actually by putting a pregenerated bitstream into the FPGA that creates a bridge between the JTAG circuitry and the flash's SPI interface.

That's exactly how it works, quoting UG908 (v2022.2), Chapter 4, p. 38:

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Attempting to Program Configuration Memory Attached to an FPGA Device
To program configuration memory attached to an FPGA device, Vivado Hardware Manager first downloads a flash controller bitstream to the FPGA device. Hardware Manager then sends flash commands and data through the FPGA device's JTAG port to be processed by the controller, which then sends the processed flash commands/data to the configuration memory interface.