And port in VHDL ON Basys 3 board

[Esmail]

I am trying to implement a VHDL design (AND gate) on the Basys 3 development borad. I create the required files but the bitstream generation faild (see the attached pictures). Also the error is attached. 

[artvvb]

Hi @Esmail

Welcome to the forums!

The property you should be setting in your constraints should be "PACKAGE_PIN" rather than "PAKAGE_PIN". This tutorial may be helpful: https://digilent.com/reference/programmable-logic/guides/getting-started-with-vivado

Thanks,

Arthur

[asmi]

1 hour ago, artvvb said:

The property you should be setting in your constraints should be "PACKAGE_PIN" rather than "PAKAGE_PIN".

That is exactly why I try to avoid writing constraints manually and instead prefer using GUI for that, as it greatly reduces chance of making silly mistakes like that one.

Edited April 28, 2023 by asmi

[artvvb]

Yeah, good point. It's also a reason to copy-paste from templates where available, though that still comes with some potential for typos.

[asmi]

18 minutes ago, artvvb said:

It's also a reason to copy-paste from templates where available, though that still comes with some potential for typos.

You can still make a typo in a pin name. But at least in GUI you will see that the signal will go to a different pin from what you had in mind.

[Esmail]

Thanks a lot for your help. When I connect the board and click open target and then Auto connect but the program device is not active,

Could you help me to complete programing the board. See the attached pictures

 

[artvvb]

Replied to the further question over here: