zzzhhh Posted April 12, 2023 Share Posted April 12, 2023 In "Getting Started with Vivado and Vitis for Baremetal Software Projects" tutorial, we are warned "Do not select the system clock input to the MIG." if MicroBlaze and DDR are used. What's wrong with the system clock? Link to comment Share on other sites More sharing options...
0 artvvb Posted April 17, 2023 Share Posted April 17, 2023 (edited) Hey @zzzhhh, sorry for the delayed response. I'm the one who wrote the guide in its current form a while back, and honestly, I'm not sure. I've been digging around in some Xilinx docs (links below), and haven't been able to come up with anything definitive so far. Perhaps using the clock would impose an otherwise unnecessary clock domain crossing on the AXI data bus connection to the MIG. Perhaps the high fanout of using the clock in many places across the design would make it more difficult to meet timing once the FPGA is more full than it is with the simple setup created in the guide. Perhaps using the clock for logic would pull it off of the CMT backbone that it needs to be on for the MIG (I don't think this one is the case, since the clock on the backbone seems like it could drive both a BUFG and a CMT/PLL?). Maybe someone with deeper experience will be able to jump in. If you build a system with Microblaze being clocked from the system clock input and don't run into any related warnings, are able to meet timing, and the clock interactions look okay, you should be good. Docs in question: https://support.xilinx.com/s/article/40603?language=en_US https://docs.xilinx.com/v/u/1.4-English/ug586_7Series_MIS, particularly "Clocking Architecture" p69 https://support.xilinx.com/s/question/0D52E00007G0d8DSAR/whats-the-meaning-of-backbone?language=en_US https://docs.xilinx.com/v/u/en-US/ug472_7Series_Clocking Hope this helped, Arthur Edited April 17, 2023 by artvvb Add ug472 zzzhhh 1 Link to comment Share on other sites More sharing options...
0 artvvb Posted April 21, 2023 Share Posted April 21, 2023 It seems that both the MIG and clocking wizard try to instantiate the input buffer (IBUFG) that the clock must pass through on its way from the pin. If these buffers were removed from generated HDL sources and placed in an RTL module feeding into both the MIG and clocking wizard, perhaps this could work, however, that could be a painful process in the tools, especially managing when those generated sources might be updated and overwritten. The "No Buffer" on input clock option in the clocking wizard would be helpful. Some related info: https://support.xilinx.com/s/question/0D52E00006hpsa9SAA/using-a-global-clock-buffer-at-a-clock-capable-pin?language=en_US And a relevant critical warning: Quote [Shape Builder 18-119] Failed to create I/OLOGIC Route Through shape for instance design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk. Found overlapping instances within the shape: design_1_i/clk_wiz_0/inst/clkin1_ibufg and design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk. Thanks, Arthur zzzhhh 1 Link to comment Share on other sites More sharing options...
0 artvvb Posted April 21, 2023 Share Posted April 21, 2023 Digging some more, the MIG configuration also allows the input clock buffer to be removed, so this might actually be doable: zzzhhh 1 Link to comment Share on other sites More sharing options...
0 asmi Posted April 21, 2023 Share Posted April 21, 2023 50 minutes ago, artvvb said: The "No Buffer" on input clock option in the clocking wizard would be helpful. There is such an option: zzzhhh and artvvb 2 Link to comment Share on other sites More sharing options...
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zzzhhh
In "Getting Started with Vivado and Vitis for Baremetal Software Projects" tutorial, we are warned "Do not select the system clock input to the MIG." if MicroBlaze and DDR are used. What's wrong with the system clock?
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