Ask for a tutorial of RISC-V on Arty A7 using Vivado and Vitis

[zzzhhh]

There is a tutorial for "Running a RISC-V Processor on the Arty A7" in Digilent webpage for Arty A7 board. But it is running on Linux, requires Arduino development environment. To aggravate the situation, an "Olimex ARM-USB-TINY-H USB Programmer" cable is needed. Since there is a "Getting Started with Vivado and Vitis for Baremetal Software Projects" alongside this RISC-V tutorial, which also uses a soft core, runs on Windows, uses Vivado and Vitis, and does not need additional hardware, I think we can also run RISC-V processor on Arty A7 with Vivado and Vitis on Windows without an Olimex ARM-USB-TINY-H USB Programmer cable. Why not? RISC-V is no special than Arm or MicroBlaze in terms of SoC development workflow. So, do you happen to know a step-by-step RISC-V tutorial (preferable in a video) similar to "Getting Started with Vivado and Vitis for Baremetal Software Projects", only with Arm or MicroBlaze replaced with RISC-V. Any RISC-V IP would be ok. Also can be either baremetal or on Linux, as long as I can follow. Thanks for your recommendation.

[artvvb]

Hi, @zzzhhh,

Unfortunately, that's the only Risc-V tutorial we've run through and tested internally. There are some other projects out there using the Arty A7, but from what I can see, most still require some form of additional kit to program the CPU once its loaded onto the board, similar to that Olimex programmer.

Thanks,

Arthur

[zzzhhh]

Thank you for the reply and recommendations therein. I have an additional question about the function of "Olimex ARM-USB-TINY-H USB Programmer". If we can use a micro-B USB cable to program FPGA and Flash on the development board through USB JTAG interface, why can't we use the same cable and interface for RISC-V programming? What is absolutely necessary to use Olimex ARM-USB-TINY-H USB Programmer instead of a USB JTAG for RISC-V programming on FPGA? Thank you.

 

 

[artvvb]

The JTAG interface is used to debug Microblaze systems with a Miicroblaze Debug Module (MDM) connected to the JTAG pins, however this capability is somewhat cooked into the tools. It might be possible to adapt the MDM debug interface to access your RISC-V processor if you can get it into a block design environment. Might also be possible to directly connect the JTAG interface, if the processor supports that, Digilent doesn't include the JTAG pins in master XDC files, but the locations may be fixed and BSCAN primitives might be usable to access them (I only have a cursory knowledge of this area). This is complicated by the fact that Digilent has made the business decision not to share the JTAG circuitry portion of our designs, and this is one of the areas affected by that. The same software used for debugging via the Olimex debugger or HS3 also doesn't necessarily support the on-board programming circuitry. 

Various other JTAG programmers that can be connected to Pmod ports could also work. Digilent also manufactures and sells some JTAG programmer components (like the JTAG HS3, which one of my colleagues indicated is also compatible with OpenOCD) that might fit the bill.

Apologies,

Arthur

[asmi]

14 hours ago, artvvb said:

Digilent doesn't include the JTAG pins in master XDC files

JTAG pins can't be included into XDC file because they are dedicated function pins, and can't be used for anything except JTAG.

14 hours ago, artvvb said:

This is complicated by the fact that Digilent has made the business decision not to share the JTAG circuitry portion of our designs, and this is one of the areas affected by that.

Which is just stupid now considering Xilinx has finally published a tool which can program FTDI's EEPROM to function just like Digilent's programmer/debugger, but it would only cost about $5 in parts instead of $50+ which Digilent charges for it's solution.

[zygot]

On 4/14/2023 at 11:07 AM, asmi said:

Which is just stupid now considering Xilinx has finally published a tool which can program FTDI's EEPROM to function just like Digilent's programmer/debugger, but it would only cost about $5 in parts instead of $50+ which Digilent charges for it's solution.

The jig has been up for a while now. Respect your customers and show them that you have some respect for yourselves. This pretense of configuration IP has gone from annoying to  sad.. and an unnecessary source of customer irritation.

[artvvb]

Passing on this feedback to hopefully start another internal conversation on the topic. Thanks.

[artvvb]

@zzzhhh

This repository should allow you to use RISC-V on an Arty A7-100T, write software for it in Vitis, and debug it over JTAG using the built-in debugging tools: https://github.com/eugene-tarassov/vivado-risc-v. I haven't run through setting it up, but the contributors seem to be affiliated with AMD/Xilinx.

Thanks,

Arthur