I want full Syntesis without Optimization.

[drkome]

I'm designing a processor architecture with RISC-V. I do synthesis and implementation with Vivado before putting it on my card. But it synthesizes and implements as much as the assembly codes in my Instruction memory. It does not synthesize the whole nucleus. It's optimizing. I dont want this. I want him to synthesize   them all. how can i fix this. I send my photo about this.  Vivado just do syntesis of addi x1,zero,5.  it didnt do of all core

[asmi]

Trust me, you DO want it to optimize. As for your specific situation - did you implement a memory? if so, synthesis and PR& would not prune anything which can affect an externally-visible state.

Besides, why are you even doing a place & route of imcomplete core? Do this in simulations until you have an actual complete core, and only then push it onto the hardware.

[drkome]

@asmiIn the future, I will want to load command to memory with uart. If nothing appears in the implementation as the memory appears to be empty, this process will not work. I am in the competition. There is a situation like loading instructions with uart in the competition. This requires compiling the entire core. The only command you see above is loaded. But the kernel executes all the commands. The more commands I pass into memory, the more it appears. I want it all to appear with uart in the operations I will do later.

[asmi]

Where that command is defined? It's supposed to be in the instruction memory BRAM cell(s), and no synthesis nor place & route will ever inspect BRAM contents as it has to way of guaranteeing that this is the only contents it will ever have, when it sees that your fetch block pulls commands from that memory. 

As a side note - most implementations of RISC-V I've seen on an Artix/Spartan-7 FPGAs run at least at 100 MHz, so UART is going to be ridiculously slow.

[drkome]

@asmi Yes! But I need this for competition. Do i have a chance to synthesize all the components? Even working signals.

[asmi]

11 minutes ago, drkome said:

@asmi Yes! But I need this for competition. Do i have a chance to synthesize all the components? Even working signals.

Again - synthesis and place&route only removes the logic which does NOT affect output. So - no, you don't need this, because presense or absense of that logic in FPGA does not change anything.

[zygot]

@drkome

I think that you are confusing the concept of optimization for logic synthesis and implementation with the kind of optimization found in a HL compiler for software that gets executed on a CPU. They are quite different animals.

If you are curious, you can read Vivado documentation about settings and strategies for synthesis and implementation. You can also just go the the project settings and view the options and settings for synthesis and implementation that you are currently using to see what's going on with your project.

Quartus has always been extremely aggressive in eliminating logic that it can't connect to what's happening on an output pin. At one point Quartus supported the concept of "virtual pins" to make life a bit easier for designers.

You can get any programmable logic vendor tool to implement everything in your design as long as you can convince the tool that everything in your design affect an output pin. It's just a matter of how you implement your design in your sources. Don't blame the tool, blame the designer....

Understand that "optimization" of logic can mean more resource usage and work at a faster clock rate. it could mean using less resources and work at a slower clock rate. If you use default strategies for synthesis and implementation then you are also telling the tools to see if they can recognize certain logic structures like counters and state machines in your code and replace whatever your source is saying with implementations that the tool prefers. The move from creating machine code that CPUs execute, to designing robust logic that works on a particular FPGA device at a particular clock rate requires a bit of conceptual re-orientation,  and perhaps quite a bit of reading.

Sometimes, mucking with the synthesis or implementation settings can make a marginal design meet timing. Usually, the best that it can do is make for some very long tool processing times and improve timing by a ns or less. As a rule, the key to making some designs work is to structure and implement your design in a way that suits the device resources and IO pin assignments. If you are making a custom board for a particular application then you need to be careful about how you design your PCB and assign pins. If you are using a general purpose FPGA board, then optimizing pin assignments isn't always possible.

Edited April 6, 2023 by zygot

[drkome]

I just write (*KEEP="true"*) in my SoC.v file, And now I get this. Thnaks for answer  @zygot @asmi 

[zygot]

The results of using source code attributes like KEEP vary from vendor to vendor, and I suppose depends on the source. Glad that you resolved your issue despite my attempt at "assistance". Except for when I use Quartus, I rarely run into problems with synthesis optimizing away my source signal names and a large chunk of my design. Such synthesis and implementation commands don't always resolve tool issues. Edited April 7, 2023 by zygot

[drkome]

@zygotI needed to get information from vivado about how many hours my processor is and its power consumption. For the competition. I can get a full clear result right now. Thank you for your help. It's good that my problem is solved for now. If this command does not work for me in other projects in the future, then I will try other ways. :) and thank you again.