drkome

I wrote my own RISCV processor. and I tested it on Zybo z7-20 board. I did not experience any problems in many tests. But I tried to do the Dhrystone test. I noticed something in the simulation when all print commands were working correctly while filling the fifo correctly. The FPGA was also causing problems while communicating with the console. See part of the image above as an example. The first 2 prints fill the UART's fifo correctly in the simulation. And the uart is created successfully. Vivado Simulation. Uart application in console. And I didnt see "ee_printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");" in this console. while it works fully and accurately in the simulation. Is there a problem with it working this way on FPGA? Is this definitely an implementation problem? I using Zybo-z7-20. I make this RTL with 20MHZ. UART spec 115200 baudrate.

@zygot Thank you very much for helping me, I learned a lot of different things while reading what you wrote. I found the problem. But I couldn't find how to solve it. But this is success for me for now. The compiler runs the lui command in the background even if I'm not using lui. As soon as the system enters the lui command. That's why the system doesn't work. LED is flashing now. The compiler adds the upper immadiate command to the li command if I type an over 11-bit number, so it doesn't work. The problem is that the lui command is a verilogal error? Is it a bug with the timer? I'm relieved to have found this now. This was my thesis project. If I hadn't found some more, I would have cried. Thank you very much for helping me. I learned a lot. WhatsApp Video 2023-07-16 at 21.19.04.mp4

@Niță Eduard thanks for try helping to me. I have control_unit.v, this module has Hazar_unit and forwarding Unit. I looked at the simulation and there is no danger and the system works in the simulation. Also, there is no problem in the simulation. All registers are added correctly and on time. Finally, I get the led output I want. If I want to light the led with only one command assembly command, I can light the led. But when the event enters the branches, the system breaks down. Branches work very well in simulation. Without any hazard. I don't understand why it doesn't work on the card. Maybe there is a problem with the reset. But I need to try ILA. OR Negedge is problem for bram ? Maybe system is working in simulation but Bram may not working in physical system.

@zygot thanks for answer, I looking this UG474, UG472 and UG471. @Niță Eduard Hello, now I try to make RV32I and pipeline architecture. Actually my project is finished. But dont work in FPGA. I will try to explain everything in order. you may be right. Maybe I can't see the led. But when I extend the timing excessively, the led lights up and it should not light up. Or not appearing at all. 1_)Since I don't have any IO outputs, I wanted to see a physical led operation. For this, I connected a bit of the outside led from the x3 register in the register file. that's my only goal right now. My constraints file 2._)By the way, I gave up on using a clock divider. I am using ClockWizard. My FGPA working at 125mhz. My clock wizard is like this. (very little loop number photos bcs of you can see pin clock edge) I knew this pin periods is very little. I am increasing the loop before embedded FPGA. This is my register file. like this because it is an infinite blink command. Here, the pin led does not light because I have increased the loop too much. It does not appear in the simulation. In the assembly command I wrote, the led does not light at first, it goes into a loop. Then the led starts to light. But when I press reset once in the system, the led lights up. Then the LED should not have been on at all. Because there is a 3b9aca00 value loop in front of it in the above register file. (Don't be confused, the pin in the other photo is made in less cycles, so the led seems to be blinking.) EDİT= I seem to understand why the problem started. It's about branching operators. But I still haven't been able to solve the problem. Let me explain how I found the error. If I write a command like above, branches, Led does not light. Because it's always in a loop. this time if i write code like above. Branch does not loop because x4 and x5 are equal. running li x3.1. BUT! If I want to count 5 times and then exit the loop and turn on the led, as in the code example above. The LED stays off. But when this branching condition appears in simulation and works correctly in simulation . The card does not work. If I saw that the led was lit only with this code, there would be no problem.

@zygot Hello! module counter1( input clk, rst, output reg [7:0] counterout ); always @ (posedge(clk), posedge(rst)) begin if (rst) counterout <= 0; else counterout <= counterout + 1; end endmodule I using this clock divider, bcs if I dont use this clock divider, My processor dont work bcs of worst slack ,that's why I using this. and this is my risc assemby instructions. I made loop code in venus(web sites), maybe I can try to raise li x4,10000000 number. x3 register is my led register. and and I left using clock divider. I using clock_wizard now. and "How did you implement this?" I dont understand this. I still new this fpga sorry. Maybe I'm asking a simple question. But it is difficult to get answers to some questions.

I gave a pin out from the register file to test it. It works very well in simulation. I have a Zybo Z-7-20 card. When I embed my project in it, it doesn't work. I programmed the blink command with assembly. In FPGA, only the light is on. In case there is a clock problem. I used a clock divider. The LED is on at first. Then it doesn't go off. But this process succeeds in simulation. If I need to send output or a document for this, I can post it. Can you help me?

@artvvb so can I fill the .hex file inside the bram with the bitstream and then embed it in the FPGA?

I was designing a RISC-V processor for my thesis project. But I decided to use BRAM. I didn't know how to load data after bitstream. I will research the keywords you provided. Thank you

BRAM structure I created as Verilog code, How do I send the data later to save it. I have a Zybo Z-7 Card. I have my own RISC-V processor. And I'm communicating with BRAM. All in verilog code format. But I want to throw code(instruction) to BRAM. How can I do that.

@zygotI needed to get information from vivado about how many hours my processor is and its power consumption. For the competition. I can get a full clear result right now. Thank you for your help. It's good that my problem is solved for now. If this command does not work for me in other projects in the future, then I will try other ways. :) and thank you again.

I just write (*KEEP="true"*) in my SoC.v file, And now I get this. Thnaks for answer @zygot @asmi

@asmi Yes! But I need this for competition. Do i have a chance to synthesize all the components? Even working signals.

@asmiIn the future, I will want to load command to memory with uart. If nothing appears in the implementation as the memory appears to be empty, this process will not work. I am in the competition. There is a situation like loading instructions with uart in the competition. This requires compiling the entire core. The only command you see above is loaded. But the kernel executes all the commands. The more commands I pass into memory, the more it appears. I want it all to appear with uart in the operations I will do later.

I'm designing a processor architecture with RISC-V. I do synthesis and implementation with Vivado before putting it on my card. But it synthesizes and implements as much as the assembly codes in my Instruction memory. It does not synthesize the whole nucleus. It's optimizing. I dont want this. I want him to synthesize them all. how can i fix this. I send my photo about this. Vivado just do syntesis of addi x1,zero,5. it didnt do of all core

@zygot, @engrpetero So thank you for help.