PMOD AD2 High Speed Mode

[harshgola00]

Hello,

 I am trying to run the PMOD AD2 ADC with Basys3 FPGA, I made it work at 100khz and 400khz, but I want to use it in HIGH SPEED MODE as described in its manual, but I am having trouble with it, 

in the timing diagram, to begin the communication

1.the first data 0x08 is sent in fast mode to all slaves, does this mean that the frequency of SCL should be 400khz?

2. the second data, after the repeated start condition, is address i.e., 0x28 with write bit(0101000) in HIGH SPEED MODE, does it require to send the write bit,  does HIGH SPEED here mean that the SCL frequency changed to 1.7Mhz (my intended HIGH SPEED FREQ)?

3. with no repeated start or stop condition(as per diagram, I could be wrong!), the 3rd data is address again with read bit, at 1.7 Mhz SCL ?

4. right after the ACK from slave, the master stretches the SCL signal (HIGH) for 2us, then the 1st byte of data is received from the slave

5. ACK from master then 2nd byte of data from slave, then NACK from master, then stop.

one transaction complete.

 

should i repeated this whole cycle every time i try to get data? or can we issue a repeated start condition after 2nd byte of data?

Thanks

 

 

Edited January 7, 2023 by harshgola00
data correction

[zygot]

The timing diagram is from the AD7991 Datasheet, so I assume that this is where you got it. If not you will want to read the datasheet very carefully because the operation of the device can be a bit confusing.

According to the datasheet, once the device is in high-speed mode it stays there until it receives a stop condition. Once conversions are started, you probably want to continue back-back conversions unless power consumption is a great concern. After a stop condition the device returns to fast mode. Be careful not to inadvertently send a stop condition by changing SDA while SCL is high. When forcing repeated conversions for one operation only frames 2 and 3 are repeated.

ADI digital interfaces for analog and mixed devices tend to be simple in implementation but complicated to use. The documentation could be clearer as well. The I2C standard uses a minimum of signals but has evolved to be somewhat complicated as well. And then not all "I2C compatible" interfaces work exactly the same way either.


Sometimes it's just easier to select a device based on how the digital interface works. Edited January 7, 2023 by zygot

[harshgola00]

Thankyou @zygot for your answer, I want to get conversion results back-to-back so power consumption won't be an issue, I want to confirm one more thing, 

 the FAST mode in the timing diagram means the SCL should be of 400 khz (right?) and when it goes into HIGH SPEED mode the SCL should be 1.7Mhz?

[zygot]

According to the timing specifications for the device SCL is up to 3.4 MHz if SCL/SDA pin loading is < 100 pF and up to 1.7 MHz if < 400 pF. The diagrams could be be better to show the change in SCL period width. Since SDA timing is dependent on SCL timing, there would be no benefit to high-speed mode if SCL didn't change its period.