harshgola00

Hello, I am new to FPGA and i have made some designs like LED on/off which used LVCMOS33 IO standards, now i am trying to output a differential signal through PMOD, and i have been told to utilize OBUFDS primitive, during the IO mapping, the IO standard available exclude the LVCMOS33 standard which i have always been using and shows DIFF_STL_18 and the like, how do i know which to choose. Thanks

Thankyou @zygot for your answer, I want to get conversion results back-to-back so power consumption won't be an issue, I want to confirm one more thing, the FAST mode in the timing diagram means the SCL should be of 400 khz (right?) and when it goes into HIGH SPEED mode the SCL should be 1.7Mhz?

Hello, I am trying to run the PMOD AD2 ADC with Basys3 FPGA, I made it work at 100khz and 400khz, but I want to use it in HIGH SPEED MODE as described in its manual, but I am having trouble with it, in the timing diagram, to begin the communication 1.the first data 0x08 is sent in fast mode to all slaves, does this mean that the frequency of SCL should be 400khz? 2. the second data, after the repeated start condition, is address i.e., 0x28 with write bit(0101000) in HIGH SPEED MODE, does it require to send the write bit, does HIGH SPEED here mean that the SCL frequency changed to 1.7Mhz (my intended HIGH SPEED FREQ)? 3. with no repeated start or stop condition(as per diagram, I could be wrong!), the 3rd data is address again with read bit, at 1.7 Mhz SCL ? 4. right after the ACK from slave, the master stretches the SCL signal (HIGH) for 2us, then the 1st byte of data is received from the slave 5. ACK from master then 2nd byte of data from slave, then NACK from master, then stop. one transaction complete. should i repeated this whole cycle every time i try to get data? or can we issue a repeated start condition after 2nd byte of data? Thanks