chclau Posted September 17, 2022 Share Posted September 17, 2022 Several VHDL code examples with source code and simulation waveform. Also, at the footer of each example, there is a link to download both the model source and testbench files from GitHub. The full list is here, and this are the individual code examples: AXI-Lite register bank Generic register with load Binary to seven-segment decoder Generic demultiplexer and decoder Generic down-counter Modulo counter Parallel to serial converter enjay and artvvb 2 Link to comment Share on other sites More sharing options...
Recommended Posts
Create an account or sign in to comment
You need to be a member in order to leave a comment
Create an account
Sign up for a new account in our community. It's easy!
Register a new accountSign in
Already have an account? Sign in here.
Sign In Now