Storing Program in Flash on CMOD A7 in 2022

[Kvass]

Hi all,

So I've been trying to store my bitstream + vitis .elf project on my CMOD A7-35t. I've done this in the past using the guide that gets referenced here often https://digilent.com/reference/learn/programmable-logic/tutorials/htsspisf/start. 

 

However, this time I'm doing it with Vivado 2020.2 and Vitis. The big change that I cannot seem to port over to Vitis is the xilisf library. This has been deprecated with Vitis and replaced with XilFlash. My CMOD board also uses Macronix flash memory. This normally means I have to do extra steps to support this memory vendor as shown in the guide.

 

 

The summary of issues I'm facing trying to store my project in flash is:

• xilisf no longer shows up in the BSP file
• I cannot configure the (non-existent) xilisf to support Macronix memory

 Is storing the project in flash memory impossible without using an older version of the SDK which supports xilisf? Does anyone have a workaround for this?

-Kvass

[JColvin]

Hi @Kvass,

I do not have a Cmod A7 with the Macronix memory to directly test this, but this is what I was able to do with the Cmod A7 I have on Vivado/Vitis 2020.2, though I did get a Microblaze application project (a barebones project that spits out "button is pressed" over a serial terminal when you press the onboard Button 1 to light up both LEDs) to load from flash.

I ended up loosely following two guides (this Instructables guide (which I wrote some more in-depth instructions for on this post here) and Adam Taylors SPI flash guide).

For the Instructables guide (and in my opinion the easier way to load a Microblaze project into flash since it doesn't use SREC at all) these are the steps that I followed:

• Spoiler

  • Create a block design with Microblaze without DDR (guide on how to do this here: https://reference.digilentinc.com/programmable-logic/guides/getting-started-with-ipi)
  • Add in the QSPI flash IP from the Board tab to the block design (usually 50 MHz clock to the external SPI clock on the AXI Quad SPI IP). Confirm that the IP confirmation on the AXI Quad IP is set to SPI Quad mode and the Slave Device is set to the flash memory that your board has.
    • If you are not certain which flash memory you have, don't worry too much. The second to last step in this list will fail if you have selected the wrong flash memory and Vivado will helpfully tell you what flash memory it actually detects as connected. (I thought my Cmod A7 had the Macronix, but Vivado instead told me it had the Micron memory, which is why I'm bringing it up)
  • Finish generating the block design, create the HDL wrapper, and generate the bitstream (or only go through Implementation).
  • Open the Implemented design, so we can do some additional configuration in the Project settings on the left-hand side under Project Manager
  • In the Project settings in the Bitstream section, set it so that the .bin file is created, go into the additional bitstream settings, set the Bitstream compression to True, set the configuration rate from 3 MHz to 33 MHz, and under Configuration Modes select Master SPI x4 (alongside the already selected JTAG). Click Ok and save the design.
  • Generate the bitsteam and export the .xsa and open Vitis.
  • Create a whatever C application project you want for your design (not SREC) and build the project. This will generate a .elf file (which can be found at <Vitis_project_location>/<application_name>/Debug/<application_name>.elf)
  • Feel free to double check your application is working in general by launching it on hardware while still in Vitis.
  • Go back to Vivado and right click on the Microblaze IP and associate the .elf under the Design sources (as opposed to simulation sources). Regenerate the bitstream (which will also generate the .bin file since we made that selection earlier).
  • Open up the Hardware Manager, click Add Configuration Memory Device, choose the flash chip associated with your board, and program it with the .bin file.
    • Again, if you do not know the flash chip, the programming operation will fail and Vivado will tell you which flash chip it detects.
  • You will need to power cycle the board (I just unplugged and then replugged the USB cable from the Cmod) but the flash memory Microblaze program should be loaded and running.

   

These are the steps that I did for Adam Taylor's SREC guide (which also does a similar association of a .elf file in Vivado):

Spoiler

• Create a block design with Microblaze without DDR (guide on how to do this here: https://reference.digilentinc.com/programmable-logic/guides/getting-started-with-ipi)
• Add in the QSPI flash IP from the Board tab to the block design (usually 50 MHz clock to the external SPI clock on the AXI Quad SPI IP). Confirm that the IP confirmation on the AXI Quad IP is set to SPI Quad mode and the Slave Device is set to the flash memory that your board has.
  • If you are not certain which flash memory you have, don't worry too much. The second to last step in this list will fail if you have selected the wrong flash memory and Vivado will helpfully tell you what flash memory it actually detects as connected. (I thought my Cmod A7 had the Macronix, but Vivado instead told me it had the Micron memory, which is why I'm bringing it up)
• Finish generating the block design, create the HDL wrapper, and generate the bitstream (or only go through Implementation).
• Open the Implemented design, so we can do some additional configuration in the Project settings on the left-hand side under Project Manager
• In the Project settings in the Bitstream section, set it so that the .bin file is created, go into the additional bitstream settings, set the Bitstream compression to True, set the configuration rate from 3 MHz to 33 MHz, and under Configuration Modes select Master SPI x4 (alongside the already selected JTAG). Click Ok and save the design.
• Generate the bitsteam and export the .xsa and open Vitis.
• Create a whatever C application project you want for your design (not SREC) and build the project. This will generate a .elf file (which can be found at <Vitis_project_location>/<application_name>/Debug/<application_name>.elf)
• Feel free to double check your application is working in general by launching it on hardware while still in Vitis.
• Create a second application project within Vitis (File -> New -> Application Project) that is based on the same platform we are currently using (probably named design_1_wrapper). Name it something different (maybe "bootloader") and choose SREC SPI Bootloader as the Template.
• Open up blconfig.h in the src folder for this bootloader and adjust the FLASH_IMAGE_BASEADDR to 0x00300000 (since that is what is recommended for the Cmod A7) and save your changes.
• Do ctrl+B to build both the regular application project and the bootloader project.
• Go to the Xilinx tab -> Program Flash
• On the Image File line, Browse for the the .elf of the application project (not the SREC bootloader). You'll see in the Console tab at the bottom of Vitis a "cmd /C mb-objcopy -O srec" followed by the location of the .elf of the application project and then the .srec version of the same application project. (This was done so you didn't have to open the Vitis shell and type in the command yourself). Click Cancel on the Program Flash Memory.
• Go back to Vivado and right click on the Microblaze IP and associate the application .elf under the Design sources (as opposed to simulation sources). Regenerate the bitstream (which will also generate the .bin file since we made that selection earlier).
• Go to Tools -> Generate Memory Configuration File
  • Set the Format to BIN, select your memory part associated with your board, and choose a location for the bin file to be generated (I put mine in the normal impl_1 folder and named it combined.bin).
  • Under the Options , set the Interface to SPIx4 (since that's what this bullet point guide did back in point 5),
  • check the "Load bitstream files" box with a Start address of all zeros, direction of up, and select the design_1_wrapper.bit file that is in <vivado_application_name>.runs/impl_1
  • Check the "Load data files" box, set the start Address to 00300000, direction up, and select the <vitis-application-name>.elf.srec. (I had to search for ".srec" in the Windows Explorer to find where the file was located).
  • Click OK.
• Open up the Hardware Manager, click Add Configuration Memory Device, choose the flash chip associated with your board, and program it with the combined.bin file (or whatever you named it)
  • Again, if you do not know the flash chip, the programming operation will fail and Vivado will tell you which flash chip it detects.
• You will need to power cycle the board (I just unplugged and then replugged the USB cable from the Cmod) but the flash memory Microblaze program should be loaded and running.

Caveat:
I'll be honest, I have no idea if this method of creating the SREC application (which didn't seem to be used?) or the special combined Memory Configuration file offers any benefit to the first method. But it works, so that's something I guess.

 

Let me know if you have any questions.

Thanks,
JColvin

[Kvass]

Hi JColvin,

I did end up using the Instructables guide to flash the memory. This seems to be a much easier way than creating the bootloader and using the SREC. No issues with the Macronix memory either. Thank you very much!

 

One thing about the guide that wasn't clear and may be worth noting is that in the guide, the .ELF file is built as a debug configuration. In practice, the MicroBlaze did not immediately run the .elf file if it was built as a debug .elf. Once I built it as a release, it worked right away. 

 

Thanks again,

-Kvass

[JColvin]

Hi @Kvass,

Thank you for pointing that out; I hadn't considered that the fact that building the project as a Debug was the reason it was not immediately launching on hardware.

Thanks,
JColvin

[Myles]

Hi All,

I have a similar problem with programming a CMod A7-15T running a project with a Microblaze and using the external SRAM and have some observations.

From my experiments in attempting to get it to work, the solution where you assign the elf to the Microblaze in the block design (as shown in the Instructables guide linked by @JColvin) works only if your Vitis application is set to run in the FPGA BRAM as set by the linker file in Vitis. If your program is larger than the BRAM and thus you have changed the linker file to have it run in external memory (such as the CMod SRAM chip), the SREC method appears to be required. In that case, the bootloader programs elf file is associated in the Vivado to Microblaze as it is set to run in the BRAM and thus loads on startup just fine. After it loads, it's job is to then load the main program from the SPI flash and into the external memory, then begin execution of it (at which point the bootloader dies... I guess).

I am having the issue in that in the new 2022 Vivado and Vitis, the xilisf library mentioned by all the SREC tutorials on the digilent website (and all others I could find) is long deprecated. So whenever they say to set the correct memory type in the BSP config to make it work, it's no longer possible as it no longer exists. Instead there is just the template application of the SPI SREC Bootloader which appears to not need that library to be added to the BSP. I have tried using this template as is via the steps @JColvin took when using Adam Taylor's SREC guide, changing only the offset memory address, and I can see on the serial port the bootloader running and attempting to load the main program. However it fails at SREC line 1 with a "line is corrupt" message. I suspect that there is further configuration that must be done to the default SPI SREC Bootloader template (much like how the config of the xilisf in the BSP included changing some values per the external memory chip) to make it work with the CMod A7 Macronix mx25l3233 QSPI flash. However my searches have so far been fruitless, and I can't seem to find out what the configuration changes should be (if any). I should point out that my project is working just fine when programmed to the FPGA via the Vitis debug system. I have also tried using both the debug and release forms of the elf files and have seen no difference.

I hope someone finds my observations helpful on what the difference between the two methods is. For my part, I am hoping someone knows how to get a CMod A7 Microblaze with an SRAM linked project (or external memory in general) to boot from flash in the new versions of Vivado/Vitis.

Thanks,
Myles

[JColvin]

Hi @Myles,

I will try to take a look into what it might take to get the actual SREC working (rather than just loading the application .elf which is what Adam Taylor's guide ultimately ends up doing). I've personally never gotten SREC process through SDK/Vitis to work on supported flash memories and know that Xilinx has depreciated the xilsf library in more recent versions of their software, so I am uncertain on amount of effort that will be required (i.e. does flash library need to be recreated).

It occurred to me that the the process I outlined adds a QSPI block to the system when a .elf is associated with Microblaze, so the QSPI portion of the design might not be required, though I do not know how much of the BRAM it takes up. Unless your design is not able to fit into the BRAM by only a small amount, attempting to optimize the design and software code will probably not be worth the effort.

Thanks,
JColvin