Myles

Hi All, I have a similar problem with programming a CMod A7-15T running a project with a Microblaze and using the external SRAM and have some observations. From my experiments in attempting to get it to work, the solution where you assign the elf to the Microblaze in the block design (as shown in the Instructables guide linked by @JColvin) works only if your Vitis application is set to run in the FPGA BRAM as set by the linker file in Vitis. If your program is larger than the BRAM and thus you have changed the linker file to have it run in external memory (such as the CMod SRAM chip), the SREC method appears to be required. In that case, the bootloader programs elf file is associated in the Vivado to Microblaze as it is set to run in the BRAM and thus loads on startup just fine. After it loads, it's job is to then load the main program from the SPI flash and into the external memory, then begin execution of it (at which point the bootloader dies... I guess). I am having the issue in that in the new 2022 Vivado and Vitis, the xilisf library mentioned by all the SREC tutorials on the digilent website (and all others I could find) is long deprecated. So whenever they say to set the correct memory type in the BSP config to make it work, it's no longer possible as it no longer exists. Instead there is just the template application of the SPI SREC Bootloader which appears to not need that library to be added to the BSP. I have tried using this template as is via the steps @JColvin took when using Adam Taylor's SREC guide, changing only the offset memory address, and I can see on the serial port the bootloader running and attempting to load the main program. However it fails at SREC line 1 with a "line is corrupt" message. I suspect that there is further configuration that must be done to the default SPI SREC Bootloader template (much like how the config of the xilisf in the BSP included changing some values per the external memory chip) to make it work with the CMod A7 Macronix mx25l3233 QSPI flash. However my searches have so far been fruitless, and I can't seem to find out what the configuration changes should be (if any). I should point out that my project is working just fine when programmed to the FPGA via the Vitis debug system. I have also tried using both the debug and release forms of the elf files and have seen no difference. I hope someone finds my observations helpful on what the difference between the two methods is. For my part, I am hoping someone knows how to get a CMod A7 Microblaze with an SRAM linked project (or external memory in general) to boot from flash in the new versions of Vivado/Vitis. Thanks, Myles