I have a problem uploading and debugging my baremetal code on the Eclypse Z7.
I'm using Vivado v2020.1 (64-bit), and Xilinx Vitis IDE v2020.1 (64-bit).
Usually it works fine but sometimes the following error message is thrown when clicking on the project -> Debug As -> Launch on Hardware: "ERROR : Memory write error at 0x119000. Asynchronous Data Abort"
This is the Vitis Log output:
14:45:30 DEBUG : Registering SDKStatusHandler to handle trace exceptions.
14:45:30 DEBUG : Registered the core plugin as the backup plugin for storing repository paths.
14:45:30 INFO : Launching XSCT server: xsct.bat -n -interactive C:\ZZZ_Projekte_Xilinx_FPGA_LOKAL\DIRCM-H_V1_Vitis\Vitis\temp_xsdb_launch_script.tcl
14:45:30 INFO : XSCT server has started successfully.
14:45:30 INFO : Successfully done setting XSCT server connection channel
14:45:30 INFO : plnx-install-location is set to ''
14:45:30 INFO : Successfully done setting workspace for the tool.
14:45:30 INFO : Platform repository initialization has completed.
14:45:31 INFO : Successfully done query RDI_DATADIR
14:45:31 INFO : Registering command handlers for Vitis TCF services
14:48:02 INFO : Connected to target on host '127.0.0.1' and port '3121'.
14:48:02 INFO : Jtag cable 'Digilent Eclypse Z7 210393AD74DAA' is selected.
14:48:02 INFO : 'jtag frequency' command is executed.
14:48:03 INFO : Context for 'APU' is selected.
14:48:03 INFO : System reset is completed.
14:48:06 INFO : 'after 3000' command is executed.
14:48:06 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent Eclypse Z7 210393AD74DAA" && level==0 && jtag_device_ctx=="jsn-Eclypse Z7-210393AD74DAA-23727093-0"}' command is executed.
14:48:08 INFO : FPGA configured successfully with bitstream "C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/DIRCM-H_V1/_ide/bitstream/design_1_wrapper.bit"
14:48:08 INFO : Context for 'APU' is selected.
14:48:08 INFO : Hardware design and registers information is loaded from 'C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa'.
14:48:08 INFO : 'configparams force-mem-access 1' command is executed.
14:48:08 INFO : Context for 'APU' is selected.
14:48:08 INFO : Sourcing of 'C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/DIRCM-H_V1/_ide/psinit/ps7_init.tcl' is done.
14:48:09 INFO : 'ps7_init' command is executed.
14:48:09 INFO : 'ps7_post_config' command is executed.
14:48:09 INFO : Context for processor 'ps7_cortexa9_0' is selected.
14:48:09 ERROR : Memory write error at 0x119000. Asynchronous Data Abort
--> The execution stops here.
Usually the error is removed by restarting the Vitis IDE, Vivado and the FPGA board but this time even restarting the computer multiple times doesn't help.
Question
gueste
Hello everyone,
I have a problem uploading and debugging my baremetal code on the Eclypse Z7.
I'm using Vivado v2020.1 (64-bit), and Xilinx Vitis IDE v2020.1 (64-bit).
Usually it works fine but sometimes the following error message is thrown when clicking on the project -> Debug As -> Launch on Hardware: "ERROR : Memory write error at 0x119000. Asynchronous Data Abort"
This is the Vitis Log output:
14:45:30 DEBUG : Registering SDKStatusHandler to handle trace exceptions.
14:45:30 DEBUG : Registered the core plugin as the backup plugin for storing repository paths.
14:45:30 INFO : Launching XSCT server: xsct.bat -n -interactive C:\ZZZ_Projekte_Xilinx_FPGA_LOKAL\DIRCM-H_V1_Vitis\Vitis\temp_xsdb_launch_script.tcl
14:45:30 INFO : XSCT server has started successfully.
14:45:30 INFO : Successfully done setting XSCT server connection channel
14:45:30 INFO : plnx-install-location is set to ''
14:45:30 INFO : Successfully done setting workspace for the tool.
14:45:30 INFO : Platform repository initialization has completed.
14:45:31 INFO : Successfully done query RDI_DATADIR
14:45:31 INFO : Registering command handlers for Vitis TCF services
14:48:02 INFO : Connected to target on host '127.0.0.1' and port '3121'.
14:48:02 INFO : Jtag cable 'Digilent Eclypse Z7 210393AD74DAA' is selected.
14:48:02 INFO : 'jtag frequency' command is executed.
14:48:03 INFO : Context for 'APU' is selected.
14:48:03 INFO : System reset is completed.
14:48:06 INFO : 'after 3000' command is executed.
14:48:06 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent Eclypse Z7 210393AD74DAA" && level==0 && jtag_device_ctx=="jsn-Eclypse Z7-210393AD74DAA-23727093-0"}' command is executed.
14:48:08 INFO : FPGA configured successfully with bitstream "C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/DIRCM-H_V1/_ide/bitstream/design_1_wrapper.bit"
14:48:08 INFO : Context for 'APU' is selected.
14:48:08 INFO : Hardware design and registers information is loaded from 'C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa'.
14:48:08 INFO : 'configparams force-mem-access 1' command is executed.
14:48:08 INFO : Context for 'APU' is selected.
14:48:08 INFO : Sourcing of 'C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/DIRCM-H_V1/_ide/psinit/ps7_init.tcl' is done.
14:48:09 INFO : 'ps7_init' command is executed.
14:48:09 INFO : 'ps7_post_config' command is executed.
14:48:09 INFO : Context for processor 'ps7_cortexa9_0' is selected.
14:48:09 ERROR : Memory write error at 0x119000. Asynchronous Data Abort
--> The execution stops here.
Usually the error is removed by restarting the Vitis IDE, Vivado and the FPGA board but this time even restarting the computer multiple times doesn't help.
I'm glad for any advice.
Thanks.
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