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Found 6 results

  1. Hello everyone, I have a problem uploading and debugging my baremetal code on the Eclypse Z7. I'm using Vivado v2020.1 (64-bit), and Xilinx Vitis IDE v2020.1 (64-bit). Usually it works fine but sometimes the following error message is thrown when clicking on the project -> Debug As -> Launch on Hardware: "ERROR : Memory write error at 0x119000. Asynchronous Data Abort" This is the Vitis Log output: 14:45:30 DEBUG : Registering SDKStatusHandler to handle trace exceptions. 14:45:30 DEBUG : Registered the core plugin as the backup plugin for storing repository paths. 14:45:30 INFO : Launching XSCT server: xsct.bat -n -interactive C:\ZZZ_Projekte_Xilinx_FPGA_LOKAL\DIRCM-H_V1_Vitis\Vitis\temp_xsdb_launch_script.tcl 14:45:30 INFO : XSCT server has started successfully. 14:45:30 INFO : Successfully done setting XSCT server connection channel 14:45:30 INFO : plnx-install-location is set to '' 14:45:30 INFO : Successfully done setting workspace for the tool. 14:45:30 INFO : Platform repository initialization has completed. 14:45:31 INFO : Successfully done query RDI_DATADIR 14:45:31 INFO : Registering command handlers for Vitis TCF services 14:48:02 INFO : Connected to target on host '' and port '3121'. 14:48:02 INFO : Jtag cable 'Digilent Eclypse Z7 210393AD74DAA' is selected. 14:48:02 INFO : 'jtag frequency' command is executed. 14:48:03 INFO : Context for 'APU' is selected. 14:48:03 INFO : System reset is completed. 14:48:06 INFO : 'after 3000' command is executed. 14:48:06 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent Eclypse Z7 210393AD74DAA" && level==0 && jtag_device_ctx=="jsn-Eclypse Z7-210393AD74DAA-23727093-0"}' command is executed. 14:48:08 INFO : FPGA configured successfully with bitstream "C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/DIRCM-H_V1/_ide/bitstream/design_1_wrapper.bit" 14:48:08 INFO : Context for 'APU' is selected. 14:48:08 INFO : Hardware design and registers information is loaded from 'C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa'. 14:48:08 INFO : 'configparams force-mem-access 1' command is executed. 14:48:08 INFO : Context for 'APU' is selected. 14:48:08 INFO : Sourcing of 'C:/ZZZ_Projekte_Xilinx_FPGA_LOKAL/DIRCM-H_V1_Vitis/Vitis/DIRCM-H_V1/_ide/psinit/ps7_init.tcl' is done. 14:48:09 INFO : 'ps7_init' command is executed. 14:48:09 INFO : 'ps7_post_config' command is executed. 14:48:09 INFO : Context for processor 'ps7_cortexa9_0' is selected. 14:48:09 ERROR : Memory write error at 0x119000. Asynchronous Data Abort --> The execution stops here. Usually the error is removed by restarting the Vitis IDE, Vivado and the FPGA board but this time even restarting the computer multiple times doesn't help. I'm glad for any advice. Thanks.
  2. I need to use the JTAG header to program the Zedboard, since the MicroUSB connector is physically damaged. I cannot find any documentation or forums about how to use the JTAG connector for programming the FPGA, so I am going to ask for your help. I have a basic design in Vivado for making switch 0 toggle led 0. The bitstream is ready to be sent to the FPGA. However, when I try to connect to the hardware, by clicking "Open target", it is unable to connect. When I try to manually connect: I am using Xilinx Platform Cable USB adapter for connecting the JTAG to the computer's USB input: I have the driver installed, and it appears in my list of devices when plugged in, and disappears if I unplug it, and is up-to-date: I suspect the jumpers may not be configured properly? But again I cannot find clear documentation on how to set this up. This is how mine is set up: Here is some information about my computer: I am using Vivado 2016.1, since that is used in a lot of the tutorials. I think the Diligent tutorial uses 2016.2. It also comes with the Zedboard board file, although I downloaded the one made by Diligent as instructed in the tutorial. I hope I have provided enough information. I appreciate any help!
  3. Hi all, I have this project to code in 8051 series, DS80C320-ECG (data source as reference): "Division of two 16 bit unsigned integers being in the internal memory, quotient and remainder should be stored". I find a way to do it but there is a part of the program that i don't understand, I attach it. I've noted which part i don't understand. By "don't understand", means that i'm not understanding why do we have to do all those calculations to find the quotient and the remainder. Is there anyone have ideas of it? Thanks in advance.
  4. I am starting with working design for the CMOD S7 where I program the device through SDK and all functionality works as intended. Now where I am falling short is getting the program to run out of the SPI Flash. I have been following the "How To Store Your SDK Project in SPI Flash" guide from Digilent in order to put a Microblaze design into SPI Flash on the CMOD S7 located at the link here: There is a recommended offset of 0x00300000 for the CMOD A7 - My question is what is the recommended offset for CMOS S7? I tried both 0x00000000 and 0x0030000 and could not get the design to work. Kind Regards, James
  5. I am interested in buying Spartan-7 FPGA Module: but first I would like to know if it suffers same USB cable issue as CMOD-A7: Since FTDI circuitries look similar on these two boards I just want to make sure the faulty design was not copied over from A7 onto S7.
  6. Hi, I am working on a project where i'm using Digilent zybo AP SoC with xilinx vivado for Hardware design and Xilinx SDK for software design. My application uses following protocol/peripherals: 1. UARTns16550 PL side (Programmable Logic) in interrupt mode. 2. GPIOs 3. Ethernet mac (lwIP stack) I started my software design using xilinx lwip perf client application project. Then i started modifying the perf client C code according to my need. My project contains Uartns16550, tcp/ip server and client program which receives real-time data. So coming to my problem, i am able to run my application from xilinx sdk GDB and system debugger. But, when i dump my code in QSPI flash and try to boot, the zybo is not booting up. I also tried loading different application project like tcp perf server, perf client. By doing this the processor boots up properly through QSPI flash. I followed the steps provided by Digilent for programming the flash and i also ensured that the jumpers are in the right place where it has to be. I believe that there's a problem with my program since i have started modifying the tcp perf client code for my project. I am not getting a clue where my code is going wrong. Operating System : Windows 10 Software : Xilinx vivado 2018.3/SDK 2018.3 Any inputs related to this will be appreciated. Thanks & Regards Ajeeth kumar