Trouble with LVDS output on a Cora Z7-10

[RyanW]

Hello, I am having some difficulties getting LVDS to output on my Cora Z7-10. I've tried boiling it down to its most basic form of just trying to output a 10Mhz clock through on one of the differentially routed PMOD ports (JA), but I'm still not seeing any output on my oscilloscope. Can anyone help in in understanding what's going wrong here? Has anyone else gotten LVDS to work correctly on this board's PMOD ports? I tried looking at some other designs like the HDMI TMDS33 through PMOD that was posted on this forum before and I was able to get TMDS33 to work with 3.3V 50 Ohm pullup resistors. Any help on this would be greatly appreciated.

This is my full constraints file:

set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports RESET] #IO_L4N_T0_35 Sch=btn[0]
set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVDS_25} [get_ports {CLKT_clk_p[0]}] #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVDS_25} [get_ports {CLKT_clk_n[0]}] #IO_L12N_T1_MRCC_34 Sch=ja_n[3]

 

This image shows all that I have in this design. I am trying to use the Vivado block diagram IP designer to instantiate the buffers, and the schematic and device view from implementation shows that the buffer is connected in the design, so I don't think the router/synthesizer is throwing it out. CLKT is using the port interface "xilinxcom:interface:diff_clock_rtl:1.0". Reset is hooked up to button 0 on this board, sys_clock is the 125MHz system clock on H16. The utility buffer IP here is configured to use an OBUFDS.

Considering I was able to get TMDS working with the pullup resistors it could be an issue with termination. I've tried it a few different ways without really seeing any output from it as well. here are the two I've tried.

My initial goal was to try and serialize parallel data from the PL, output it over LVDS on some wires back into the PL with SERDES primitives and see how fast I could get reliable transmission, but I'm not able to get any LVDS out, so I need to solve that bit first. I do have two of these devices, so it would be fun to transmit from one to the other as well.

Edited February 24, 2022 by RyanW

[thinkthinkthink]

The JA pins are on Bank 34 which is supplied from VCC3V3 (page 8 of the Cora Z7 schematic) so no way you could do 2.5 V.

[thinkthinkthink]

The Eclypse Z7 and the ZedBoard can do LVDS_25 but only on pins that are routed to the SYZYGY connectors (on the Eclypse) and to the FMC LPC connector (on the ZedBoard) which would mean you'd need a custom SYZYGY pod or FMC module to access those pins.

The only boards with a PMOD port connected to a FPGA bank supplied by an adjustable voltage source are the Genesys ZU variants.

[RyanW]

That would explain quite a lot, I thought that VCC was able to be changed from internal electronics using the Xilinx constraints; I'm new to the ins and outs of FPGAs so I assumed wrongly. So each bank needs to be externally supplied at the desired VCC? Does Digilent offer any Zynq based boards with VCC2V5 or a way to reconfigure the voltage supplied to individual banks from board selection jumpers/programmable power ICs?

Thank you so much for your response as well, I've nearly gone crazy trying to figure this one out.