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Found 7 results

  1. Hello, I am having some difficulties getting LVDS to output on my Cora Z7-10. I've tried boiling it down to its most basic form of just trying to output a 10Mhz clock through on one of the differentially routed PMOD ports (JA), but I'm still not seeing any output on my oscilloscope. Can anyone help in in understanding what's going wrong here? Has anyone else gotten LVDS to work correctly on this board's PMOD ports? I tried looking at some other designs like the HDMI TMDS33 through PMOD that was posted on this forum before and I was able to get TMDS33 to work with 3.3V 50 Ohm pullup resistors. Any help on this would be greatly appreciated. This is my full constraints file: set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports RESET] #IO_L4N_T0_35 Sch=btn[0] set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVDS_25} [get_ports {CLKT_clk_p[0]}] #IO_L12P_T1_MRCC_34 Sch=ja_p[3] set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVDS_25} [get_ports {CLKT_clk_n[0]}] #IO_L12N_T1_MRCC_34 Sch=ja_n[3] This image shows all that I have in this design. I am trying to use the Vivado block diagram IP designer to instantiate the buffers, and the schematic and device view from implementation shows that the buffer is connected in the design, so I don't think the router/synthesizer is throwing it out. CLKT is using the port interface "xilinxcom:interface:diff_clock_rtl:1.0". Reset is hooked up to button 0 on this board, sys_clock is the 125MHz system clock on H16. The utility buffer IP here is configured to use an OBUFDS. Considering I was able to get TMDS working with the pullup resistors it could be an issue with termination. I've tried it a few different ways without really seeing any output from it as well. here are the two I've tried. My initial goal was to try and serialize parallel data from the PL, output it over LVDS on some wires back into the PL with SERDES primitives and see how fast I could get reliable transmission, but I'm not able to get any LVDS out, so I need to solve that bit first. I do have two of these devices, so it would be fun to transmit from one to the other as well.
  2. Hi, Background: I am sending 3 channels of digitized 12-bit (soon to be 16-bit) data over "long" distances (thus I will be sending the data using LVDS). I will also be sending a 40 Mhz clock signal over LVDS so in total, that will be 3 data channels + 1 clock (= 4 channels x 2 wires/channel = 8 wires). The data rate is 600-720 Mbps per channel for 12-bit and up to 960Mbps per channel for 16-bit for the data lines. Question(s): I would like to use the HDMI connector on the Z7-20 board to get the data in. Is that possible? If so, I would appreciate any information as to how to go about doing this. HDMI has a number of LVDS lines (actually TDMS) and I would like to take advantage of the built in hardware to include deserialization of the data and memory storage. TDMS uses 9/10 bit data but I will use 12 bit to 16 bits. Is the data size fixed in hardware or would I be able to configure that? I'm new to FPGAs but can the data get pipelined directly into memory? If so, is there a way to set the bit endianness as it gets stored into memory? If the above is solvable, I would like to know if I can use both HDMI connectors to do this (I will actually have 2 sensors), both the HDMI in and HDMI out. In theory I just need the data lines and access to memory so I wouldn't think that this would be a problem on the HDMI out as well, but I don't know...which is why I'm asking. If the above isn't possible, are there any other options? I can make an adapter board and deserialize the data to CMOS/TTL digital IO and use the PMOD or shield connectors to send the data to the FPGA but this would be 12 bits/channel x 3 channels = 36 bits at 40 Mhz, (48 bits for 16 bit data). That doesn't leave me very many (or any) lines for output but if that is my only option, is 40 Mhz considered high speed? Thanks in advance.
  3. So, I want to bring in a 100 MHz clock and route it to a CMT to generate a bunch of lower frequency clocks all phase-locked to the 100 MHz. I appreciate I can't output an LVDS signal, but it looks like I should be able to bring in an LVDS signal as long as I supply my own 100 ohm termination to pins 18 and 19 for example. Am I missing anything? Paul Smith Indiana University Physics
  4. I am seeking an FPGA-based solution to communicate with a commercial display driver via mini-LVDS, which is a unidirectional interface specification established by Texas Instruments. From my understanding of the Artix-7 documentation, transmitting mini-LVDS signals is possible by exercising the MINI_LVDS_25 I/O standard on any HR I/O bank, so long as the desired bank VCCO = 2.5V. I possess an Arty S7 board, which appears to have high-speed JA and JB PMOD ports for high-speed protocols such as LVDS. However, Vcco for bank voltages 0, 14, and 15 are set to 3.3V, but both mini-LVDS and LVDS mandate 2.5V rail voltage in 7Series devices. Is it possible to alter the feedback resistor network for FB1 (shown on pg. 10 of to convert Vcco 3.3V to 2.5V? I believe by reducing R200 from 31.6K to 21.5K, 2.5V output from channel 1 of ADP5052 is achievable. Please confirm that there are no unintended consequences here. Also, I worry about signal integrity when routing differential pairs through standard 0.1" pin headers. Is this a valid concern for my frequencies of interest (50 ~ 200MHz)? I appreciate your input.
  5. I'm using a CMOD S7 board and I intend to use a couple of LVDS output pairs. I set the output pairs in Vivado as LVDS_25* and it is regularly synthesized. But I don't see any output on those pairs, and it is probably due to the power supply to the FPGA bank involved. My question is: can I use this kind of LVDS output on this evaluation board?
  6. Hi there! I'm trying to make differential clock(100MHz from oscillator) to differential clock output(40MHz differential) clk_100M_P&M is connected to external crystal oscillator(input) and I allocated clk_40_P&M to PIO port(output). clk_front , clk_back is for check point. when I checked, the result was : clk_front : 100MHz & clk_back : 40MHz . However, clk_40_P &N port didn't output some waveform. I have no idea what's the problem. 1st trial : clk_front & back : LVCmos33 and clk_40_P & N : LVDS25 -> result : LVCmos33,(bank34) clk_front & back (success) and (bank35) clk_40_P & N : LVDS25 ( failed ) 2nd trial : clk_front & back : LVCmos25 and clk_40_P & N : LVDS25 -> result : LVCmos25 ,(bank35) clk_front & back (success) and (bank35) clk_40_P & N : LVDS25 ( failed ) thank you for your help!
  7. Hello, I am trying to implement LVDS (1.2V nominal) using the Digilent Arty-S7 25 board. The schematic shows that the JA and JB Pmod connectors have 4 diff. pairs per connector. However, it looks like VCCO (the power supply for this I/O bank) is tied to 3.3V. To my knowledge, there is no differential I/O protocol that uses 3.3V. Does this mean that JA and JB can't be used for differential pairs? (Wouldn't that negate the point of running the differential pairs in the first place?) Or do the pins just output the correct voltage when you implement the LVDS protocol? Please help! Thank you