zedboard Connecting the uartlite signals from the PL through Pmod pins on a ZedBoard

[Daniel Glasser]

In Vivado (2021.2) I have created a new project for the ZedBoard that includes:

• MicroBlaze in microcontroller configuration with 128KiB local memory
• AXI interrupt controller
• AXI timer
• AXI GPIO (x2)
• MicroBlaze Debug Module
• UARTlite

When I use the design assistant, the uartlite external signals (collectively, "uart_rtl)" are not connected to any IO pins and place design fails. I wrote some constraints to assign 'uart_rtl_rxd" to Pmod connection JA3 and "uart_rtl_txd" to Pmod connection JA4 (FPGA pins Y10 and AA9, respectively):

set_property PACKAGE_PIN Y10  [get_ports {uart_rtl_rxd}];  # "JA3"
set_property PACKAGE_PIN AA9  [get_ports {uart_rtl_txd}];  # "JA4"

Now I get the following during placement ("Implementation/Place Design/Pin Planning/IO Standard"):

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13. For example, the following 
two ports in this bank have conflicting VCCOs: 
uart_rtl_rxd (LVCMOS18, requiring VCCO=1.800) and sys_clock (LVCMOS33, requiring VCCO=3.300)

All of the Pmod connections for the PL appear to be in Bank 13, which is 3.3v, so I am looking for a way to tell Vivado that I want "uart_rtl_rxd" and "uart_rtl_txd" to be 3.3V, and while I'm at it, add any necessary pull-ups/pull-downs.

I found out about the "Pmod bridge" IP and installed the unpacked "vivado-library-zmod-v1-2091.1-2" into the IP repositories, and have tried to add "pmod bridge 1.1", routed the "tx_0" and "rx_0" from the UART Lite as I saw in one example, but can't figure out how to assign the "Pmod_out_0" I end up with to a specific Pmod connector. The tutorial at https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/2018.2 indicates that the "board" tab should have the Pmod interfaces listed, but they don't appear for the ZedBoard.

I have attached the block design that removed the direct connection of the uartlite tx and rx signals to pins and added the Diligent Pmod Bridge IP as "tutorial_1.tcl".

I am really out of my depth here.  I will continue to seek answers via Google and forum searches, but any suggestions would be appreciated.

Thanks.

tutorial_1.tcl

[thinkthinkthink]

set_property -dict { PACKAGE_PIN Y10 IOSTANDARD LVCMOS33 } [get_ports {uart_rtl_rxd}]; # "JA3"

set_property -dict { PACKAGE_PIN AA9 IOSTANDARD LVCMOS33 } [get_ports {uart_rtl_txd}]; # "JA4"

Here, fixed your constraints for you, it's that easy.