Arty z7 zynq 7000-20: could not print hello world at vitis serial terminal

[Rai Taimoor Ali]

hi, I have followed the Getting Started with FPGA Design #1-4: Embedded C Application Basics in FPGAs by Digilent youtube Chanel.  I have complete the steps as per instructed in videos but could not get the hello world at terminal. The output what i get

 

Hardware Arty z7 20

vivado 2021.1

Output:

Connected to COM4 at 115200
Initializing...
init:done
Arty Z7 -Z20 Rev. B Demo Image

 

it would be great if anyone can help me out.

I have also attached the screen shot.

Thanks 

[JColvin]

Hi @Rai Taimoor Ali,

I'll need to go through this particular series of videos to see how the project was set up (I didn't personally make the material); the block design looks fine (though you do not need the clocking wizard IP) and the main function should be fine. I'll try this out tomorrow to see what I learn.

Thanks,
JColvin

[ia2022]

I am having the exact same problem with recently bought Arty z7-20 and Vitis 2021.2. I was trying this tutorial. I couldn't resolve it. Then I switched to Vivado 2018.1. It worked fine with Vivado 2018.1. I am wondering whether Vitis 2021.x has overlooked/missed support for Arty z7-20 board or not. Please let me know when it works.

Thanks,

IA

Edited January 19, 2022 by ia2022
typo

[thinkthinkthink]

Have you tried other serial terminals like TeraTerm or Putty ?

[ia2022]

I am using ubuntu 20.04. I have tried cutecom. It only shows "... Rev. B Demo Image". Same as the first post. With Vivado 2018.1 I can see xil_printf("...") in cutecom.

I believe Vitis sends/generates something different from what older Vivado used to send/generate. That might make things not work in Vitis.

[Rai Taimoor Ali]

I dont know could not figure it out yet why this things happen. Although by a simple project involving processes and  fixed IOs print hello world works. still looking for the answer.

[artvvb]

It looks like the print statements seen on the console are coming from the Arty Z7's out-of-box demo, programmed into flash during manufacturing. Please change the boot mode jumper (JP4) from QSPI to JTAG. While QSPI mode does not prevent JTAG programming, it does prevent QSPI programming, which will make it a little more obvious whether the hello world app is being programmed in or not.

Could you provide a screenshot of the Vitis Log tab after trying to run the demo? It should show some launch scripts getting run, targeting the Arty Z7, see attached for an example (though this not the same application or board).

Thanks,

Arthur

[HaveBlue]

@Rai Taimoor Ali Since xil_printf works but not print, you may want to check your BSP settings to make sure stdin/stdout are redirected to the UART rather than the JTAG DCC channel. The default appears to have changed in Vitis 2021.X.

 If you open up the .spr:

and got to "Modify BSP Settings", then go to Overview/standalone:

Make sure the value for stdin/stdout are your UART and not ps7_coresight_comp_0.

[Rai Taimoor Ali]

@artvvbYes, you are right, print statements seen on the console are coming from the Arty Z7's out-of-box demo problem solved by changing the boot mode jumper (JP4) from QSPI to JTAG.

Thanks,