Rai Taimoor Ali

and if i put uart_output(); sleep(1); uart_output(); i get the whole string but for every printf comand in main i need to put sleep(1); which mean if system is getting the values every 10ms then i will lose most the readings.

@JColvin Thank you sir for the quick response. basically the idea is to send 5 int and 5 short int values as a single string to PC. And because the reading of these 10 variables will change as per the system response so string values and length always change.

Sir @JColvin and @artvvb need help. Thanks

I am trying to send data from arty z7-7020 board to PC using uart through a function (driver xuartps.h). within the main program, the code works but calling it from function, output at putty gets overlapped. i tried to debug the code but it looks fine and get output as expected. Need help. thanks code: #include "platform.h" #include "xil_printf.h" #include<stdlib.h> #include "xuartps.h" void uart_output(){ char *p; char tip[100]=" hi : uart_text_multiple time \n\r\0"; u32 transmittedBytes; u32 totalTransmittedBytes; u32 status; u16 byteCnt; XUartPs_Config *PiUartConfig; XUartPs PiUart; byteCnt=0; PiUartConfig=XUartPs_LookupConfig(XPAR_PS7_UART_0_DEVICE_ID); status = XUartPs_CfgInitialize(&PiUart,PiUartConfig, PiUartConfig->BaseAddress); if(status!=XST_SUCCESS) print("Uart initialization failed...\n\r"); status = XUartPs_SetBaudRate(&PiUart, 115200); if(status!=XST_SUCCESS) print("BaudRATE init failed....\n\r"); int o; o=0; p =tip; while(*p != '\0'){ byteCnt+=1; p++; } do{ totalTransmittedBytes=0; p =tip; while( totalTransmittedBytes<byteCnt+2){ transmittedBytes = XUartPs_Send(&PiUart, (u8*)&p[totalTransmittedBytes],byteCnt); totalTransmittedBytes += transmittedBytes; } p++; o++; }while(o<10); } int main() { init_platform(); uart_output(); uart_output(); cleanup_platform(); return 0; }

@JColvin thanks you sir. link helped a lot.

I am trying to implement rgb oled using ip core provided by digilent in arty z7-20 using JA pmod connector. critical warnings(31): [IP_Flow 19-4965] IP PmodOLEDrgb_axi_quad_spi_0_0 was packaged with board value 'digilentinc.com:arty:part0:1.1'. Current project's board value is 'digilentinc.com:arty-z7-20:part0:1.0'. Please update the project settings to match the packaged IP. [IP_Flow 19-4965] IP PmodOLEDrgb_axi_gpio_0_1 was packaged with board value 'digilentinc.com:arty:part0:1.1'. Current project's board value is 'digilentinc.com:arty-z7-20:part0:1.0'. Please update the project settings to match the packaged IP. [IP_Flow 19-4965] IP PmodOLEDrgb_pmod_bridge_0_0 was packaged with board value 'digilentinc.com:arty:part0:1.1'. Current project's board value is 'digilentinc.com:arty-z7-20:part0:1.0'. Please update the project settings to match the packaged IP. [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values.

@artvvbYes, you are right, print statements seen on the console are coming from the Arty Z7's out-of-box demo problem solved by changing the boot mode jumper (JP4) from QSPI to JTAG. Thanks,

I have also tried to re create custom ip as shown in above picture with proper architecture, completed the block diagram and generate bit stream with no critical errors but could not succeeded to implement simple hello world application in vitis. is this because vivado or vitis thing? Thanks in advance.

Thanks for the quick response @artvvb and yest you are right moving of project between two computer is done through copy and paste. I should have use export function to create zip file of project. Thanks for the reply.

[Board 49-67] The board_part definition was not found for digilentinc.com:arty-z7-20:part0:1.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.

I dont know could not figure it out yet why this things happen. Although by a simple project involving processes and fixed IOs print hello world works. still looking for the answer.

Project is already working on lab pc. but opening in personal pc encounter this error. it will be great if anyone can help me in this regards.Thanks C:/ProjCPCw22/cpbase/vitiswsp/artyz7_system/export/artyz7_system/sw/artyz7_system/boot/fsbl.elf

hi, I have followed the Getting Started with FPGA Design #1-4: Embedded C Application Basics in FPGAs by Digilent youtube Chanel. I have complete the steps as per instructed in videos but could not get the hello world at terminal. The output what i get Hardware Arty z7 20 vivado 2021.1 Output: Connected to COM4 at 115200 Initializing... init:done Arty Z7 -Z20 Rev. B Demo Image it would be great if anyone can help me out. I have also attached the screen shot. Thanks